A4985SESTR-T Allegro Microsystems Inc, A4985SESTR-T Datasheet
A4985SESTR-T
Specifications of A4985SESTR-T
Available stocks
Related parts for A4985SESTR-T
A4985SESTR-T Summary of contents
Page 1
DMOS Microstepping Driver with Translator Features and Benefits ▪ Low R outputs DS(ON) ▪ Automatic current decay mode detection/selection ▪ Mixed and Slow current decay modes ▪ Synchronous rectification for low power dissipation ▪ Internal UVLO ▪ Crossover-current protection ▪ ...
Page 2
... Special power-on sequencing is not required. Selection Guide Part Number A4985SESTR-T 24-contact QFN with exposed thermal pad A4985SETTR-T 32-contact QFN with exposed thermal pad A4985SLPTR-T 24-pin TSSOP with exposed thermal pad ...
Page 3
A4985 VREG VDD Current Regulator REF DAC PWM Latch Blanking Mixed Decay STEP DIR RESET Control Translator Logic MS1 MS2 PWM Latch ENABLE Blanking Mixed Decay SLEEP DAC V REF DMOS Microstepping Driver with Translator Functional Block Diagram 0.22 F ...
Page 4
A4985 ELECTRICAL CHARACTERISTICS Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Body Diode Forward Voltage Motor Supply Current Logic Supply Current Control Logic Logic Input Voltage Logic Input Current Microstep Select Logic Input Hysteresis ...
Page 5
A4985 THERMAL CHARACTERISTICS may require derating at maximum conditions Characteristic Symbol Package Thermal Resistance *In still air. Additional thermal information available on Allegro Web site. DMOS Microstepping Driver with Translator Test Conditions* ES package; estimated, on 4-layer PCB, based on ...
Page 6
A4985 STEP MS1, MS2, RESET, or DIR STEP minimum, HIGH pulse width STEP minimum, LOW pulse width Setup time, input change to STEP Hold time, input change to STEP Figure 1. Logic Interface Timing Diagram Table 1. Microstep Resolution Truth ...
Page 7
A4985 The A4985 is a complete microstepping Device Operation. motor driver with a built-in translator for easy operation with minimal control lines designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step resolution modes. The currents ...
Page 8
A4985 Slow Mixed Decay Decay Missed Step Voltage on ROSC terminal 2 V/div. Step input 10 V/div. Figure 2. Missed steps in low-speed microstepping I 500 mA/div. LOAD Step input 10 V/div. Figure 3. Continuous stepping using automatically-selected mixed stepping ...
Page 9
A4985 turns off either the source FET (when in Slow Decay Mode) or the sink and source FETs (when in Mixed Decay Mode). The maximum value of current limiting is set by the selection of R and the voltage at ...
Page 10
A4985 Capacitor values should be Class 2 dielectric ±15% maximum, or tolerance R, according to EIA (Electronic Industries Alliance) specifications. ( ¯ E ¯ ¯ N ¯ ¯ A ¯ ¯ B ¯ ¯ L ¯ ¯ E ¯ ) ...
Page 11
A4985 V STEP 100.00 70.71 I OUT 0 –70.71 –100.00 I OUT Symbol I Figure 7. Current Decay Modes Timing Chart DMOS Microstepping Driver with Translator See Enlargement A Enlargement PEAK Characteristic t Device fixed off-time ...
Page 12
A4985 Layout. The printed circuit board should use a heavy ground- plane. For optimum electrical and thermal performance, the A4985 must be soldered directly onto the board. On the under- side of the A4985 package is an exposed pad, which ...
Page 13
A4985 C3 GND U1 C4 GND C5 ROSC C1 GND GND GND VDD DMOS Microstepping Driver with Translator And Overcurrent Protection OUT2B C6 GND OUT2A R4 R5 OUT1A GND OUT1B BULK GND CAPACITANCE C2 VBB LP package typical application and ...
Page 14
A4985 VDD VBB 8 V GND GND V BB VREG SENSE 10 V GND DMOS Microstepping Driver with Translator Pin Circuit Diagrams GND PGND GND MS1 MS2 DIR V REG VREF ROSC DMOS SLEEP Parasitic GND And ...
Page 15
A4985 STEP 100.00 70.71 Phase 1 I OUT1A 0.00 Direction = H (%) –70.71 –100.00 100.00 70.71 Phase 2 I OUT2A 0.00 Direction = H (%) –70.71 –100.00 Figure 8. Decay Mode for Full-Step Increments STEP Phase 1 I OUT1A ...
Page 16
A4985 STEP 100.00 92.39 83.15 70.71 55.56 38.27 Phase 1 19.51 I OUT1A 0.00 Direction = H –19.51 (%) –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 100.00 92.39 83.15 70.71 55.56 38.27 Phase 2 19.51 I OUT2B 0.00 Direction = H ...
Page 17
A4985 Table 2. Step Sequencing Settings Home microstep position at Step Angle 45º; DIR = H DMOS Microstepping Driver with Translator Phase 1 Full Half 1/4 1/8 Current Step Step Step Step [% I tripMax ] # # # # ...
Page 18
A4985 ES Package OUT2B 1 18 ENABLE 2 17 GND 3 16 PAD CP1 4 15 CP2 5 14 VCP 6 13 Terminal List Table Name ES CP1 4 CP2 5 DIR 17 ¯ E ¯ ¯ N ¯ ¯ ...
Page 19
A4985 ES Package, 24-Pin QFN with Exposed Thermal Pad 4.00 ±0. 25X 0.08 C +0.05 0.25 –0.07 0.50 BSC 0.45 MAX DMOS Microstepping Driver with Translator 4.00 ±0.15 C SEATING PLANE 0.75 ...
Page 20
A4985 ET Package, 32-Contact QFN with Exposed Thermal Pad 33X 0.08 C 0.25±0.10 0.50±0. DMOS Microstepping Driver with Translator 5.00 ±0. 5.00 ±0.15 C SEATING PLANE 0.90 ±0.10 C ...
Page 21
A4985 LP Package, 24-Pin TSSOP with Exposed Thermal Pad 7.80 ±0. 4.32±0.05 24X 0.10 C +0.05 0.25 0.65 –0.06 DMOS Microstepping Driver with Translator And Overcurrent Protection 4° ±4 0.15 3.00±0.05 4.40 ±0.10 6.40 ±0.20 ...
Page 22
A4985 Revision History Revision Rev. 1 Copyright ©2009-2011, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec tions as may be required to ...