PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet
PACCLK5406D-S-EVN
Specifications of PACCLK5406D-S-EVN
Related parts for PACCLK5406D-S-EVN
PACCLK5406D-S-EVN Summary of contents
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Evaluation Board User’s Guide July 2010 Revision: EB50_01.2 ...
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... The evalu- ation board can be used stand-alone to review the performance and in-system programmability of the ispClock5406D device companion board and clock source for LatticeECP3™ FPGA evaluation boards: • LatticeECP3 Serial Protocol Board • ...
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... The ispClock5400D Evaluation Board is 100% lead free and RoHS compliant as Lattice Semiconductor Corpora- tion is sensitive to environmental issues. Additional resources relating to the ispClock5400D Evaluation Board are available on the Lattice web site. Go to: www.latticesemi/.com/boards and navigate to the appropriate link. Updates to this document can be found there, as well as sample programs and links to other related items ...
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... Video Reference Clock – A co-demonstration with the LatticeECP3 Video Protocol board. Note possible that you will obtain your evaluation board after it has been reprogrammed. To restore the factory default demo and program it with other Lattice-supplied examples, see the Download Demo Designs section of this document. ...
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... Lattice Semiconductor 2. Set DIP switches SW1 3 and 4 ON and all other switches OFF. The blue LOCK LED lights to indicate the on-chip PLL is stable and locked to a reference clock. 3. Start PAC-Designer. 4. Choose File > Open… The Open dialog appears. 5. Browse the Base_Demo_CLK5406D.PAC project and choose Open. ...
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... Lattice Semiconductor 9. If the board is not programmed with the demo project yet, press the Download icon on the top toolbar. Figure 4. PAC-Designer Top Toolbar The Frequency Summary dialog appears and reports the Reference and VCO frequency settings. Figure 5. Frequency Summary Dialog Box 10. Click OK. ...
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... Lattice Semiconductor Figure 6. Scope Plot - Four Differential Outputs Note: For user-designed boards and other applications, refer to the data sheet configurations and the schematics of Appendix A. The schematic shows different resistor combinations for the different output bank settings. In LVDS mode the schematic uses a single 100 Ohm resistor between each BANK_P and BANK_N pin as a fully differential output ...
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... Lattice Semiconductor Figure 7. Scope Plot - Bank 0 and Bank 2 Overlapped Note that a small inherent skew of the outputs plus any set-up delay in cables is about 50-80ps PAC-Designer choose Tools > Design Utilities… The Design Utilities dialog appears. 3. Choose ispPAC-CLK54_Skew_Editor.exe and click OK. The ISPPAC-CLK5406D Skew Editor appears. ...
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... Lattice Semiconductor 4. Position the mouse over the rising edge of the Bank2 Time waveform. The cursor will changes to a double-arrow icon to indicate a waveform edit. 5. Click and hold the Bank 2 Time waveform, then drag it three units to the right. The Setting field displays 3 and Time Skew (ps) displays 54.00. ...
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... Lattice Semiconductor Invert Clock Output This section describes the procedure to invert the ispClock5406D output. In this procedure you will use the ispClock5406D Invert feature to invert Bank2 output. To invert a clock output: 1. From the PAC-Designer schematic view, double-click the BANK_2+/BANK_2- Output Block. ...
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... Lattice Semiconductor Figure 11. Scope Plot - Inverted Output Bank 6. Repeat steps 1-4 to adjust the output bank to not invert the output (Inverted = No) and reprogram the device. Modify Clock Phase Skew This section describes the procedure to modify phase skew of the ispClock5406D output. The Phase skew Unit Delay (PUD ...
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... Lattice Semiconductor Figure 12. Scope Plot - Phase Skew Adjustment The waveform shows the BANK_2 output advanced 1.24 ns. Modify the Reference Clock Source Input The evaluation board provides both 100 MHz (REFA) and 156.25 MHz (REFB) reference clock sources using on- board CMOS oscillators. This section demonstrates active clock selection using the ispClock5406D user-program- mable control and status USER pins, to adjust the on-chip REFSEL signal ...
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... Lattice Semiconductor Figure 13. Scope Plot - 156.25 MHz Output The 156.25 MHz clock from the REFB input output appears on the scope. 6. Toggle position 3 of the DIP switch (USER3) on the evaluation board back to the 1=REF-SEL position to enable the 100 MHz input reference clock, REFA_P/N input. ...
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... Lattice Semiconductor Figure 14. Design Utilities Dialog Box 6. Select ispClock_5406_I2C_Utility.exe and click OK. 2 The ispClock5406D I C Utility appears. 2 Figure 15. ispClock5406D I C Utility 7. Choose Options > I2C Interface… The Cable and I/O Port Setup Dialog appears. ispClock5400D Evaluation Board 14 User’s Guide ...
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... Lattice Semiconductor 8. Click the Change… button until the Uses PC USB Port title appears. 9. Disable the Bypass Hardware Checking (Demo Mode) option. 10. Click the Settings… button. The USB Settings dialog appears. 11. From the Select USB port name… section, choose Search for download cable on all USB ports and click Connect Now. ...
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... Lattice Semiconductor Figure 17. Scope Plot - Skew Measurement Note a small inherent skew of the outputs plus any set-up delay in cables is about 50-80ps From the ispClock5406D I C Utility click the Output Group 1 button. The ispClock5406D Output Group 1 Control dialog appears. Figure 18. ispClock5406D Output Group 1 Control ...
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... Lattice Semiconductor - Ref Select, reference MUX control - Phase–Skew value, 16 values - Output Delay Mode for Zero-Delay mode or FOB, Fan-Out Buffer mode 4. Double-click the Bank 2 output block (0x0, 8 TUD, 0=Disable) of the schematic. The Output Group-1 Bank 2 Time Skew dialog appears. 5. Specify 3 and click OK. ...
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... Lattice Semiconductor Figure 20. ispClock5406D Soft Reset Dialog - Soft Reset Released State 4. Click OK. Note the scope display changes to reflect the time-skewed waveform pattern produced earlier. I will be retained and reapplied after soft reset has been released. 5. Click the Full Reset button. ...
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... Lattice Semiconductor 5. Specify REF Frequency: 100 then click the Internal Feedback, Modify... button. The External Feedback Setting dialog appears. 6. Select Internal Feedback, select Feedback taken from V-Divider 8, and click OK. 7. From the PLL Core Settings dialog, click OK. 8. From the Edit Symbol dialog, select USER PINS and click the Edit... button. ...
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... Driving SERDES Devices with the ispClock5400D Differential Clock mance characteristics of the ispClock5406D clock output in the context of a XAUI application. SMA connections J29, J33 and J30, J34 of the LatticeECP3 Serial Protocol Board allow you to connect the SMA outputs of the ispClock5400D Evaluation Board as high-quality clock source. ...
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... PAC-Designer software. Programming for the ispClock5406D device is controlled using PAC-Designer or the ispVM System software, avail- able for download from the Lattice website at www.latticesemi.com/ispvm. Refer to the ispVM System software for help regarding operation of this software. JTAG programming is supported with the eight-pin connector J14 and either the Lattice ispDOWNLOAD USB download cable (HW-USBN-2A, provided) or the parallel download cable (HW-DLN-3C) ...
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... Lattice Semiconductor Figure 21. Change Programming Cable Interface Dialog Box 4. From the Programming Cable Interface list, select Uses PC USB and click OK. The Cable and I/O Port Setup dialog appears. Figure 22. Cable and I/O Port Setup Dialog Box 5. Click Settings… ...
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... Lattice Semiconductor Figure 23. USB Settings Dialog Box 6. Enable Connect at startup and click OK. An information dialog appears. After altering the USB setting within these dialog boxes, PAC-Designer must be restarted to load the port drivers for the system. Figure 24. PAC-Designer JTAG Prompt 7. Click OK to dismiss the message. ...
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... Lattice Semiconductor Figure 25. Frequency Summary Dialog Box 4. Click OK. PAC-Designer reprograms the evaluation board with the updated JEDEC programming file. ispClock5400D Evaluation Board This section describes the features of the ispClock5400D Evaluation Board in detail. The features appear in alpha- betical order. DIP Switch To simplify the use of the evaluation board an 8-position DIP switch (SW1) is provided for common adjustments ...
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... Lattice Semiconductor The ispClock5406D can also be driven from an external differential clock source by moving the zero-ohm resistor from the R35 location to the R37 location and connecting the clocks to both REFB_N and REFB_P inputs (J1 and J2). When an external clock source is used, switches 1 and 2 of DIP-switch SW1 (Appendix A, Figure 34) should be in the left position to disable both on-board oscillators ...
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... Lattice Semiconductor Figure 27. Bank 0 MLVDS with On-Board Termination ispClock R16 0 MLVDS R18 100 Buffers R17 0 ispClock5406D Standard Evaluation Board LVPECL LVPECL drivers require a DC bias at the driven end of the T-Line and 100 ohms differential termination at the receiving end of the T-Line. The DC bias is usually provided by 50 ohms impedance to VCCO-2V. This will both bias the output buffers and terminate one end of the T-Line to minimize reflections ...
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... Lattice Semiconductor Figure 29. Bank 0 SSTL15/SSTL18 with On Board Termination ispClock R16 20 SSTL Buffers R17 20 ispClock5406D Standard Evaluation Board SSTL25 Figure 30 shows the only difference from SSLT15/SSTL18 and SSTL25 is the source termination R16 and R17 increases from 20 ohms to 25 ohms. The remainder of the circuit is the same as SSTL15/SSTL18, discussed above ...
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... Lattice Semiconductor HCSL HCSL termination involves a bias network to ground at the driver and no termination at the end of the T-Line. Figure 32 shows the drivers biased through series resistors R16 and R17 (value of 33 ohms) combined with resis- tors R19 and R20 (value of 50 ohms). R19 and R20 also provide T-Line source termination. The receiving end of the T-Line does not require any termination ...
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... Lattice Semiconductor ispClock_5400_I2C_OutGroup_Sch.emf ispClock_5400_I2C_PLL_Sch.emf 2 5. Rerun the ispClock5406D I C Utility. Environmental Requirements The evaluation board must be stored between -40°C and 100°C. The recommended operating temperature is between 0°C and 55°C. The evaluation board can be damaged without proper anti-static handling. Pin Information and Bank Summary This section describes the pin information for the ispClock5406D device and board connections ...
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... LatticeECP3 Serial Protocol Board User’s Guide • EB39: LatticeECP3 Video Protocol Board User’s Guide Ordering Information Description ispClock5400D Evaluation Board Pin Function version 01.2, November 2009. Ordering Part Number PACCLK5406D-S-EVN 30 ispClock5400D Evaluation Board User’s Guide Bank Board Connection 0 BANK_0N 0 ...
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... December 2009 July 2010 © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor Appendix A. Schematic Figure 33. ispClock5406D VCCA 23 VCCJ 37 VCCD 44 ispClock5400D Evaluation Board GNDA 13 GNDD 43 DIE_PAD 49 32 User’s Guide ...
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... Lattice Semiconductor Figure 34. ispClock5406D Reference Oscillator “A” ispClock5400D Evaluation Board 33 User’s Guide ...
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... Lattice Semiconductor Figure 35. ispClock5406D Reference Oscillator “B” ispClock5400D Evaluation Board 34 User’s Guide ...
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... Lattice Semiconductor Figure 36. ispClock5406D Output Bank 0 Termination and Connectors ispClock5400D Evaluation Board 35 User’s Guide ...
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... Lattice Semiconductor Figure 37. ispClock5406D Output Bank 2 Termination and Connectors ispClock5400D Evaluation Board 36 User’s Guide ...
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... Lattice Semiconductor Figure 38. ispClock5406D Output Bank 3 Termination and Connectors ispClock5400D Evaluation Board 37 User’s Guide ...
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... Lattice Semiconductor Figure 39. ispClock5406D Output Bank 5 Termination and Connectors ispClock5400D Evaluation Board 38 User’s Guide ...
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... Lattice Semiconductor Figure 40. +12V to +5V Input 3.3V VCC Output and VCCO Adjustable Enb 2 GND ispClock5400D Evaluation Board User’s Guide Enb 2 GND 1 ...
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... Lattice Semiconductor 2 Figure 41. Test, JTAG and I C Interface and Connectors ispClock5400D Evaluation Board User’s Guide ...
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... Lattice Semiconductor Appendix B. Bill of Materials Table 3. Bill of Materials Item Quantity Reference C13, C12, C15, C18, C21, C24 C26, C30-31, C35-45, C46, C47 C6, C9, C27, C34, C49 4 7 C5, C8, C48, C50- C13, C16, C19, C22 6 7 C10, C11, C14, C17, C20, C23, C28 0.01uF SMD 0805 ceramic capacitor C0805C103K5RACTU ...
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... Lattice Semiconductor Table 3. Bill of Materials (Continued) Item Quantity Reference N/A ispClock5400D Evaluation Board Part NPN Trans. SOT-23 NPN Trans. SOT-223 ispPAC-CLK5406D 3.3V fixed regulator SMD 8SOIC Adj LDO Regulator SMD 8SOIC 74LVC3G34 Triple Buffer 8-SSOP 3M Rubber Bump-ons (P416) 3M Static Bag 5X8 50F7150 Extra Nut for J11 & ...