EA-OEM-204 Embedded Artists, EA-OEM-204 Datasheet
EA-OEM-204
Specifications of EA-OEM-204
Related parts for EA-OEM-204
EA-OEM-204 Summary of contents
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... CPU to execute sequential instructions from flash memory at the maximum 72 MHz system clock rate. This feature is available only on the LPC2000 ARM microcontroller family of products. The LPC2478, with real-time debug interfaces that include both JTAG and embedded trace, can execute both 32-bit ARM and 16-bit Thumb instructions ...
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... Four general purpose timers/counters with 8 capture inputs and 10 compare outputs. Each timer block has an external count input. Two PWM/timer blocks with support for three-phase motor control. Each PWM has an external count inputs. RTC with separate power domain. Clock source can be the RTC oscillator or the APB clock ...
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... LPC2478FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 × 15 × LPC2478 Product data sheet Description plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm 0.7 mm All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 September 2010 ...
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NXP Semiconductors 4.1 Ordering options Table 2. Ordering options Type number Flash SRAM (kB) (kB) LPC2478FBD208 512 LPC2478FET208 512 LPC2478 Product data sheet External Ethernet USB bus OTG/ OHC/ device + 4 ...
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... AHB AHB BRIDGE BRIDGE 16 kB MASTER AHB TO SLAVE SRAM PORT AHB BRIDGE PORT AHB TO APB BRIDGE REAL- TIME CLOCK All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 September 2010 Single-chip 16-bit/32-bit microcontroller XTAL1 XTAL2 V DD(3V3) V DDA RESET DBGEN SYSTEM ...
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... Pinning information 6.1 Pinning Fig 2. LPC2478 pinning LQFP208 package Fig 3. LPC2478 pinning TFBGA208 package Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 P3[27]/D27/ 2 CAP1[0]/PWM1[4] 5 P1[4]/ENET_TX_EN 6 9 P1[17]/ENET_MDIO 10 LPC2478 Product data sheet 1 LPC2478FBD208 52 ball A1 index area LPC2478FET208 ...
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NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol 13 P3[20]/D20/ 14 PWM0[5]/DSR1 17 P1[5]/ENET_TX_ER/ MCIPWR/PWM0[3] Row B 1 P3[2]/ P1[1]/ENET_TXD1 6 9 P4[25]/ DD(3V3) 17 P2[0]/PWM1[1]/TXD1/ TRACECLK/LCDPWR Row C 1 P3[13]/D13 ...
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NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol 14 P4[11]/A11 15 Row G 1 P3[5]/ n.c. 15 Row H 1 P0[23]/AD0[0]/ 2 I2SRX_CLK/CAP3[ SSIO Row J 1 P3[6]/ P0[16]/RXD1/ 15 ...
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NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol 9 P1[23]/USB_RX_DP1/ 10 LCDVD[9]/LCDVD[13]/ PWM1[4]/MISO0 13 P2[15]/CS3/ 14 CAP2[1]/SCL1 17 V DD(3V3) Row R 1 P0[12]/USB_PPWR2/ 2 MISO1/AD0[6] 5 P3[24]/D24/ 6 CAP0[1]/PWM1[ SSIO 13 P2[17]/RAS 14 ...
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... LPC2478 Product data sheet Type Description I/O Port 0: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. [1] I/O P0[0] — General purpose digital input/output pin. ...
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... MAT2[2] — Match output for Timer 2, channel 2. [1] I/O P0[9] — General purpose digital input/output pin. 2 I/O I2STX_SDA — transmit data driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I [17] specification. O LCDVD[17] — LCD data. I/O MOSI1 — Master Out Slave In for SSP1. ...
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... SDA1 — data input/output (this is not an open-drain pin). [1] I/O P0[20] — General purpose digital input/output pin. O DTR1 — Data Terminal Ready output for UART1. I/O MCICMD — Command line for SD/MMC interface. 2 I/O SCL1 — clock input/output (this is not an open-drain pin). ...
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... P0[31] — General purpose digital input/output pin. I/O USB_D+2 — USB port 2 bidirectional D+ line. I/O Port 1: Port bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. [1] I/O P1[0] — ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P1[3]/ 177 A10 ENET_TXD3/ MCICMD/ PWM0[2] [1] P1[4]/ 192 A5 ENET_TX_EN [1] P1[5]/ 156 A17 ENET_TX_ER/ MCIPWR/ PWM0[3] [1] P1[6]/ 171 B11 ENET_TX_CLK/ MCIDAT0/ PWM0[4] [1] P1[7]/ 153 D14 ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P1[16]/ 180 D10 ENET_MDC [1] P1[17]/ 178 A9 ENET_MDIO [1] P1[18 USB_UP_LED1/ PWM1[1]/CAP1[0] [1] P1[19 USB_TX_E1/ USB_PPWR1/ CAP1[1] [1] P1[20 USB_TX_DP1/ LCDVD[6]/ LCDVD[10]/ ...
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... I AD0[5] — A/D converter 0, input 5. I/O Port 2: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. All information provided in this document is subject to legal disclaimers. ...
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... LCDENAB/LCDM — STN AC bias drive or TFT data enable output. [1] I/O P2[5] — General purpose digital input/output pin. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. O DTR1 — Data Terminal Ready output for UART1. O TRACEPKT0 — Trace Packet, bit 0. O LCDLP — Line synchronization pulse (STN). Horizontal synchronization [19] pulse (TFT). ...
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... EINT3 — External interrupt 3 input. O LCDVD[5]/LCDVD[9]/LCDVD[19] — LCD data. I/O MCIDAT3 — Data line 3 for SD/MMC interface. I/O I2STX_SDA — Transmit data driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I [6] I/O P2[14] — General purpose digital input/output pin. O CS2 — ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P2[16]/CAS 87 R11 [1] P2[17]/RAS 95 R13 [1] P2[18 CLKOUT0 [1] P2[19 CLKOUT1 [1] P2[20]/DYCS0 73 T8 [1] P2[21]/DYCS1 81 U11 [1] P2[22]/DYCS2/ 85 U12 ...
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... I/O SCL2 — clock input/output (this is not an open-drain pin). I/O Port 3: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. [1] I/O P3[0] — General purpose digital input/output pin. ...
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... P3[21] — General purpose digital input/output pin. I/O D21 — External memory data line 21. O PWM0[6] — Pulse Width Modulator 0, output 6. O DTR1 — Data Terminal Ready output for UART1. [1] I/O P3[22] — General purpose digital input/output pin. I/O D22 — External memory data line 22. ...
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... D31 — External memory data line 31. O MAT1[2] — Match output for Timer 1, channel 2. I/O Port 4: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. [1] I/O P4[0] — ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P4[7]/A7 121 L16 [1] P4[8]/A8 127 J17 [1] P4[9]/A9 131 H17 [1] P4[10]/A10 135 G17 [1] P4[11]/A11 145 F14 [1] P4[12]/A12 149 C16 [1] P4[13]/A13 155 B16 [1] P4[14]/A14 ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P4[23]/A23/ 129 J15 RXD2/MOSI1 [1] P4[24]/OE 183 B8 [1] P4[25]/WE 179 B9 [1] P4[26]/BLS0 119 L15 [1] P4[27]/BLS1 139 G15 [1] P4[28]/BLS2/ 170 C11 MAT2[0]/LCDVD[6]/ LCDVD[10]/ LCDVD[2]/ TXD3 [1] ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [7] RESET 35 M2 [8][9] XTAL1 44 M4 [8][9] XTAL2 46 N4 [8][10] RTCX1 34 K2 [8][10] RTCX2 33, 63, L3, T5, SSIO 77, 93, R9, P12, ...
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NXP Semiconductors [5] Pad provides digital I/O and USB functions designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). [ tolerant pad with 5 ns glitch filter providing digital I/O functions ...
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... AHB address space. Lower speed peripheral functions are connected to the APB. The AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is allocated address space within the APB address space. ...
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... It may be programmed In System via the serial port (UART0). The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field and firmware upgrades. The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at speeds of 72 MHz ...
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... RAM 0x4000 0000 - 0x4000 FFFF 0x7FE0 0000 - 0x7FE0 3FFF 0x7FD0 0000 - 0x7FD0 3FFF off-chip Memory four static memory banks each 0x8000 0000 - 0x80FF FFFF 0x8100 0000 - 0x81FF FFFF 0x8200 0000 - 0x82FF FFFF 0x8300 0000 - 0x83FF FFFF four dynamic memory banks, 256 MB each ...
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... Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor ...
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... NXP Semiconductors service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a programmable interrupt priority ...
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... Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. Each DMA channel has a specific hardware priority. ...
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... Power-down mode. Each enabled interrupt can be used to wake the chip up from Power-down mode. 7.9.1 Features • Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. • Direction control of individual bits. • ...
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... LCD panel clock may be generated from the peripheral clock, or from a clock input pin. 7.11 Ethernet The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity ...
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... Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. • Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. ...
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... The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers ...
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... CAN buses in industrial or automotive applications. Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN Library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the ARM environment. The main operational difference is ...
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... Burst conversion mode for single or multiple inputs • Optional conversion on transition of input pin or Timer Match signal • Individual result registers for each ADC channel to reduce interrupt overhead 7.15 10-bit DAC The DAC allows the LPC2478 to generate a variable analog output. The maximum output value of the DAC is V 7.15.1 Features • ...
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... Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.18.1 Features • ...
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... The I C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed ...
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... NXP Semiconductors 7.21.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1, 48) kHz. • ...
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... NXP Semiconductors 7.23 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2478. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers ...
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... RTC and battery RAM The RTC is a set of counters for measuring time when system power is on, and optionally when power is off. It uses little power in Power-down and Deep power-down modes. On the LPC2478, the RTC can be clocked by a separate 32.768 kHz oscillator programmable prescale divider based on the APB clock ...
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... Crystal oscillators The LPC2478 includes three independent oscillators. These are the Main Oscillator, the Internal RC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the PLL and ultimately the CPU. ...
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... This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down and Deep power-down modes, any wake-up of the processor from Power-down modes makes use of the Wake-up Timer ...
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... In addition, Peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. ...
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... NXP Semiconductors the meantime, the flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 μs flash start-up time. When it times out, access to the flash will be allowed. The customers need to reconfigure the PLL and clock dividers accordingly. 7.26.4.4 Deep power-down mode Deep power-down mode is similar to the Power-down mode, but now the on-chip regulator that supplies power to the internal logic is also shut off ...
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... V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts Reset to inactivate the LPC2478 when ...
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... NXP Semiconductors CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. 7.27.4 AHB The LPC2478 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB SRAM ...
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... RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2478 contain a specific configuration of RealMonitor software programmed into the on-chip ROM memory ...
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... The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise noted ...
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NXP Semiconductors 9. Thermal characteristics The average chip junction temperature, T equation amb • T amb • R th(j-a) • The internal power dissipation is the product of I the I/O pins is often ...
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NXP Semiconductors 10. Static characteristics Table 8. Static characteristics = −40 °C to +85 °C for commercial applications, unless otherwise specified. T amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter DD(DCDC)(3V3) supply voltage (3 ...
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... I pull-down current pd I pull-up current C-bus pins (P0[27] and P0[28]) V HIGH-level input IH voltage V LOW-level input IL voltage V hysteresis voltage hys V LOW-level output OL voltage I input leakage current LI LPC2478 Product data sheet …continued Conditions pull- pull-down I DD(3V3 DD(3V3) no pull-up/down −(0.5V ) < V < DD(3V3 ...
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... DD(3V3) [7] 3-state outputs go into 3-state mode when V [8] Please also see the errata note in errata sheet. [9] Accounts for 100 mV voltage drop in all supply lines. [10] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [11] Minimum condition for ...
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NXP Semiconductors 10.1 Power-down mode I DD(IO) (μA) Fig 5. I (μA) Fig 6. LPC2478 Product data sheet −2 −4 −40 − 3 i(VBAT) DD(DCDC)(3V3) amb I/O maximum supply current I ...
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NXP Semiconductors I DD(DCDC)pd(3v3) Fig 7. 10.2 Deep power-down mode I DD(IO) (μA) Fig 8. LPC2478 Product data sheet 800 (μA) 600 400 V = 3.3 V DD(DCDC)(3V3) 200 V = 3.0 V DD(DCDC)(3V3) 0 −40 − ...
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NXP Semiconductors I (μA) Fig 9. I DD(DCDC)dpd(3v3) Fig 10. Total DC-to-DC converter maximum supply current I LPC2478 Product data sheet 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 −15 V ...
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NXP Semiconductors 10.3 Electrical pin characteristics V Fig 11. Typical HIGH-level output voltage V (mA) Fig 12. Typical LOW-level output current I LPC2478 Product data sheet 3 °C 25 °C 3.2 −40 °C 2.8 2.4 ...
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... Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. [2] [3] Bus capacitance C in pF, from 400 pF. b Fig 13. External clock timing (with an amplitude of at least V LPC2478 Product data sheet over specified ranges. DD(3V3) Conditions V ...
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NXP Semiconductors 11.1 Internal oscillators Table 10. Dynamic characteristic: internal oscillators = −40 °C to +85 °C; 3.0 V ≤ amb Symbol Parameter f internal RC oscillator frequency osc(RC) f RTC input frequency i(RTC) [1] Parameters are valid ...
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... Number of program/erase cycles. [2] t specified for < 1 ppm. ret LPC2478 Product data sheet = 3 3.6 V; all voltages are measured with respect to DD(3V3) Conditions [1] [2] powered; < 100 cycles unpowered; < 100 cycles All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 September 2010 ...
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... Table 14. Dynamic characteristics: Static external memory interface = −40 ° ° pF amb DD(DCDC)(3V3) Symbol Parameter Conditions [1] Common to read and write cycles t CS LOW to address valid CSLAV time [1][2] Read cycle parameters t OE LOW to address valid OELAV time t CS LOW to OE LOW time ...
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... ⁄ cy(CCLK) CCLK [4] Latest of address valid, CS LOW, OE LOW to data valid. [5] Earliest of CS HIGH, OE HIGH, address change to data invalid. [6] Byte lane state bit (PB …continued = 3.6 V, AHB clock = 1 MHz DD(3V3) Min Typ [3] 0.78 2.54 −0.29 [3] 0.20 [3] 0 2.54 Max Unit 5 ...
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... See Figure 18. LPC2478 Product data sheet = 3.6 V, AHB clock = 1 MHz, EMC Dynamic Read DD(DCDC)(3V3) DD(3V3) Conditions All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 September 2010 LPC2478 Single-chip 16-bit/32-bit microcontroller Min Typ ...
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... NXP Semiconductors 11.7 Timing CS addr data t CSLOEL OE BLS Fig 14. External memory read access CS BLS/WE addr data OE Fig 15. External memory write access LPC2478 Product data sheet t CSLAV OELAV t OELOEH t BLSLAV t CSLAV t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV All information provided in this document is subject to legal disclaimers. ...
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NXP Semiconductors T PERIOD differential data lines Fig 16. Differential data-to-EOP transition skew and EOP width shifting edges SCK MOSI MISO Fig 17. MISO line set-up time in SSP Master mode Fig 18. Signal timing LPC2478 Product data sheet crossover ...
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... Figure 20. LPC2478 Product data sheet Conditions ) is the difference between the actual step width and the ideal step width. See ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after Figure 19. Figure Figure 19. All information provided in this document is subject to legal disclaimers. ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 19. ADC characteristics LPC2478 Product data sheet (2) (5) (4) (3) 1 LSB (ideal (LSB ...
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NXP Semiconductors AD0[y] Fig 20. Suggested ADC interface - LPC2478 AD0[y] pin LPC2478 Product data sheet LPC2XXX 20 kΩ SAMPLE SSIO, SSCORE All information provided in this document is subject to legal disclaimers. Rev. ...
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... NXP Semiconductors 13. DAC electrical characteristics Table 17. DAC electrical characteristics = −40 °C to +85 °C unless otherwise specified DDA amb Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G C load capacitance L R load resistance L LPC2478 Product data sheet Conditions All information provided in this document is subject to legal disclaimers ...
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NXP Semiconductors 14. Application information 14.1 LCD panel signal usage Table 18. LCD panel connections for STN single panel mode External pin 4-bit mono STN single panel LPC2478 pin used LCDVD[23] - LCDVD[22] - LCDVD[21] - LCDVD[20] - LCDVD[19] - ...
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NXP Semiconductors Table 19. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel LPC2478 pin used LCDVD[23] - LCDVD[22] - LCDVD[21] - LCDVD[20] - LCDVD[19] - LCDVD[18] - LCDVD[17] - LCDVD[16] - LCDVD[15] - ...
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NXP Semiconductors Table 20. LCD panel connections for TFT panels External TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) pin LPC2478 LCD pin used function [4] LCDVD[23] P1[29] BLUE3 [4] LCDVD[22] P1[28] BLUE2 [4] LCDVD[21] P1[27] BLUE1 [4] ...
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NXP Semiconductors 14.2 Suggested USB interface solutions LPC24XX Fig 21. LPC2478 USB interface on a self-powered device LPC24XX Fig 22. LPC2478 USB interface on a bus-powered device LPC2478 Product data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1.5 kΩ ...
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NXP Semiconductors RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D−1 USB_UP_LED1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 23. LPC2478 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2478 Product data sheet ...
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NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC24XX USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 24. LPC2478 USB OTG port configuration: VP_VM mode LPC2478 Product data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1302 ADR/PSW ...
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NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 V BUS Fig 25. LPC2478 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2478 Product data sheet Ω 33 Ω ...
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NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 26. LPC2478 USB OTG port configuration: USB port 1 host, USB port 2 host 14.3 Crystal oscillator XTAL input and component selection The input ...
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... NXP Semiconductors In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in ...
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NXP Semiconductors Table 22. Fundamental oscillation frequency F 15 MHz to 20 MHz 20 MHz to 25 MHz 14.4 RTC 32 kHz oscillator component selection Fig 29. RTC oscillator modes and models: oscillation mode of operation and external The RTC ...
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... Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input The default configuration for standard I/O pins is input with pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. pin configured as digital output pin configured ...
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NXP Semiconductors 14.7 Reset pin configuration Fig 31. Reset pin configuration LPC2478 Product data sheet reset GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 September 2010 LPC2478 Single-chip ...
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... NXP Semiconductors 15. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 1 156 157 pin 1 index 208 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.8 0.5 mm 1.2 0.3 0.6 0.4 OUTLINE VERSION IEC SOT950-1 Fig 33. Package outline SOT950-1 (TFBGA208) ...
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... Acronym list Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Byte Lane Select BrownOut Detection Controller Area Network Digital-to-Analog Converter Debug Communication Channel Direct Memory Access End Of Packet Embedded Trace Macrocell General Purpose General Purpose Input/Output ...
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... Section 14.4 “RTC 32 kHz oscillator component Section 14.5 “XTAL and RTCX Printed Circuit Board (PCB) layout Section 14.6 “Standard I/O pin configuration” Section 14.7 “Reset pin configuration” Figure 13 “External clock timing (with an amplitude of at least V Table 9 “Dynamic characteristics”. Figure 19 “ADC characteristics” ...
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... NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’ ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s 19. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC2478 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... USB device controller . . . . . . . . . . . . . . . . . . . 36 7.12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.12.2 USB host controller 7.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.12.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 37 7.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.13 CAN controller and acceptance filters . . . . . . 37 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.14 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.15 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.16 UARTs 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.17 SPI serial I/O controller ...
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... Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Single-chip 16-bit/32-bit microcontroller Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2478 All rights reserved ...