KSZ8863RLL-EVAL Micrel Inc, KSZ8863RLL-EVAL Datasheet - Page 10

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KSZ8863RLL-EVAL

Manufacturer Part Number
KSZ8863RLL-EVAL
Description
BOARD EVALUATION FOR KSZ8863RLL
Manufacturer
Micrel Inc
Datasheet

Specifications of KSZ8863RLL-EVAL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
576-3868
Micrel, Inc.
KSZ8863MLL/FLL/RLL
List of Tables
Table 1. FX Signal Threshold.........................................................................................................................................17
Table 2. MDI/MDI-X Pin Definitions ...............................................................................................................................17
Table 3. Internal Function Block Status ..........................................................................................................................22
Table 4. MII Signals .......................................................................................................................................................27
Table 5. RMII Clock Setting ............................................................................................................................................28
Table 6. RMII Signal Description....................................................................................................................................29
Table 7. RMII Signal Connections..................................................................................................................................29
Table 8. MII Management Interface Frame Format .......................................................................................................30
Table 9. Serial Management Interface (SMI) Frame Format .........................................................................................31
Table 10. FID+DA Lookup in VLAN Mode .....................................................................................................................32
Table 11. FID+SA Lookup in VLAN Mode .....................................................................................................................32
Table 12. Spanning Tree States ....................................................................................................................................34
Table 13. SPI Connections ............................................................................................................................................39
Table 14. Data Rate Limit Table ....................................................................................................................................60
Table 16. Format of Static VLAN Table (16 Entries)......................................................................................................82
Table 17. Format of Dynamic MAC Address Table (1K Entries) ...................................................................................83
Table 18. Format of “Per Port” MIB Counters ................................................................................................................84
Table 19. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets............................................................................85
Table 20. Format of “All Port Dropped Packet” MIB Counters.......................................................................................85
Table 22. EEPROM Timing Parameters ........................................................................................................................89
Table 23. MAC Mode MII Timing Parameters................................................................................................................90
Table 24. PHY Mode MII Timing Parameters ................................................................................................................91
Table 25. RMII Timing Parameters ................................................................................................................................92
Table 26. I2C Timing Parameters ..................................................................................................................................94
Table 27. SPI Input Timing Parameters.........................................................................................................................95
Table 28. SPI Output Timing Parameters ......................................................................................................................96
Table 29. Auto-Negotiation Timing Parameters.............................................................................................................97
Table 31. Transformer Selection Criteria .....................................................................................................................100
Table 32. Qualified Single Port Magnetics...................................................................................................................100
Table 33. Typical Reference Crystal Characteristics ...................................................................................................100
November 2009
10
M9999-110309-1.1

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