KSZ8863RLL-EVAL Micrel Inc, KSZ8863RLL-EVAL Datasheet - Page 33

• Manufacturer Part Number: KSZ8863RLL-EVAL
• Description: BOARD EVALUATION FOR KSZ8863RLL
• Manufacturer: Micrel Inc

Specifications of KSZ8863RLL-EVAL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3868

Micrel, Inc.
KSZ8863MLL/FLL/RLL
Figure 6. 802.1p Priority Field Format
802.1p-based priority is enabled by bit [5] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively.
The KSZ8863MLL/FLL/RLL provides the option to insert or remove the priority tagged frame's header at each individual
egress port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2-byte Tag Control Information field
(TCI), is also referred to as the IEEE 802.1Q VLAN tag.
Tag Insertion is enabled by bit [2] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. At the egress port,
untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in register sets {19,20},
{35,36} and {51,52} for ports 1, 2 and 3, respectively and the source port VID has to be inserted at selected egress ports
by bit[5:0] of register 194. The KSZ8863MLL/FLL/RLL will not add tags to already tagged packets.
Tag Removal is enabled by bit [1] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. At the egress port, tagged
packets will have their 802.1Q VLAN Tags removed. The KSZ8863MLL/FLL/RLL will not modify untagged packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p Priority Field Re-mapping is a QoS feature that allows the KSZ8863MLL/FLL/RLL to set the “User Priority
Ceiling” at any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority
field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field.
DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (registers 96 to 111) in the Advanced Control Registers section. The ToS
priority control registers implement a fully decoded, 64-bit Differentiated Services Code Point (DSCP) register to
determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are
fully decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the DSCP register to
determine priority.
Spanning Tree Support
To support spanning tree, port 3 is designated as the processor port.
The other ports (port 1 and port 2) can be configured in one of the five spanning tree states via “transmit enable”, “receive
enable” and “learning disable” register settings in registers 18 and 34 for ports 1 and 2, respectively. The following table
shows the port setting and software actions taken for each of the five spanning tree states.
November 2009
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