KSZ8863RLL-EVAL Micrel Inc, KSZ8863RLL-EVAL Datasheet - Page 39

no-image

KSZ8863RLL-EVAL

Manufacturer Part Number
KSZ8863RLL-EVAL
Description
BOARD EVALUATION FOR KSZ8863RLL
Manufacturer
Micrel Inc
Datasheet

Specifications of KSZ8863RLL-EVAL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
576-3868
Micrel, Inc.
The KSZ8863MLL/FLL/RLL is capable of supporting a SPI bus.
The following is a sample procedure for programming the KSZ8863MLL/FLL/RLL using the SPI bus:
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power down”
can be programmed after the switch has been started.
The following four figures illustrate the SPI data cycles for “Write”, “Read”, “Multiple Write” and “Multiple Read”. The read
data is registered out of SPIQ on the falling edge of SPIC, and the data input on SPID is registered on the rising edge of
SPIC.
November 2009
1. At the board level, connect the KSZ8863MLL/FLL/RLL pins as follows:
2. Enable SPI slave mode by setting the KSZ8863MLL/FLL/RLL strap-in pins PS[1:0] to “10”.
3. Power up the board and assert reset to the KSZ8863MLL/FLL/RLL.
4. Configure the desired register settings in the KSZ8863MLL/FLL/RLL, using the SPI write or multiple write
5. Read back and verify the register settings in the KSZ8863MLL/FLL/RLL, using the SPI read or multiple read
command.
command.
KSZ8863MLL/FLL/RLL Pin #
39
36
37
38
KSZ8863MLL/FLL/RLL Signal Name
SPISN
SCL
(SPIC)
SDA
(SPID)
SPIQ
Figure 10. SPI Write Data Cycle
Figure 11. SPI Read Data Cycle
Table 13. SPI Connections
39
External Processor Signal Description
SPI Slave Select
SPI Clock
SPI Data
(Master output; Slave input)
SPI Data
(Master input; Slave output)
KSZ8863MLL/FLL/RLL
M9999-110309-1.1

Related parts for KSZ8863RLL-EVAL