KSZ8863RLL-EVAL Micrel Inc, KSZ8863RLL-EVAL Datasheet - Page 9

• Manufacturer Part Number: KSZ8863RLL-EVAL
• Description: BOARD EVALUATION FOR KSZ8863RLL
• Manufacturer: Micrel Inc

Specifications of KSZ8863RLL-EVAL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3868

Micrel, Inc.
KSZ8863MLL/FLL/RLL
List of Figures
Figure 1. Typical Straight Cable Connection .................................................................................................................18
Figure 2. Typical Crossover Cable Connection .............................................................................................................19
Figure 3. Auto-Negotiation and Parallel Operation ........................................................................................................20
Figure 4. Destination Address Lookup Flow Chart, Stage 1..........................................................................................24
Figure 5. Destination Address Resolution Flow Chart, Stage 2.....................................................................................25
Figure 6. 802.1p Priority Field Format ...........................................................................................................................33
Figure 7. Tail Tag Frame Format ...................................................................................................................................35
Figure 8. Tail Tag Rules.................................................................................................................................................35
Figure 9. EEPROM Configuration Timing Diagram .......................................................................................................37
Figure 10. SPI Write Data Cycle ....................................................................................................................................39
Figure 11. SPI Read Data Cycle ....................................................................................................................................39
Figure 12. SPI Multiple Write .........................................................................................................................................40
Figure 13. SPI Multiple Read .........................................................................................................................................40
Figure 14. Far-End Loopback Path ................................................................................................................................41
Figure 15. Near-end (Remote) Loopback Path..............................................................................................................42
Figure 16. EEPROM Interface Input Timing Diagram....................................................................................................89
Figure 17. EEPROM Interface Output Timing Diagram .................................................................................................89
Figure 18. MAC Mode MII Timing – Data Received from MII ........................................................................................90
Figure 19. MAC Mode MII Timing – Data Transmitted to MII .......................................................................................90
Figure 20. PHY Mode MII Timing – Data Received from MII.........................................................................................91
Figure 21. PHY Mode MII Timing – Data Transmitted to MII.........................................................................................91
Figure 22. RMII Timing – Data Received from RMII ......................................................................................................92
Figure 23. RMII Timing – Data Transmitted to RMII ......................................................................................................92
Figure 24. I2C Input Timing............................................................................................................................................93
Figure 25. I2C Start Bit Timing.......................................................................................................................................93
Figure 28. SPI Input Timing ...........................................................................................................................................95
Figure 29. SPI Output Timing.........................................................................................................................................96
Figure 30. Auto-Negotiation Timing ...............................................................................................................................97
Figure 31. Reset Timing.................................................................................................................................................98
Figure 32. Recommended Reset Circuit........................................................................................................................99
Figure 33. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output................................................99
Figure 34. 48-Pin LQFP (LQ) .......................................................................................................................................101
November 2009
9
M9999-110309-1.1