LFE3-95EA-PCIE-DKN Lattice, LFE3-95EA-PCIE-DKN Datasheet - Page 16

• Manufacturer Part Number: LFE3-95EA-PCIE-DKN
• Description: MCU, MPU & DSP Development Tools LatticeECP3-95EA PCI Express Dev Kit
• Manufacturer: Lattice
• Series: ECP3r

Specifications of LFE3-95EA-PCIE-DKN

• Silicon Manufacturer: Lattice Semiconductor
• Silicon Family Name: LatticeECP3
• Kit Contents: Board
• Features: On-board Boot Flash, Switches, LEDs, Displays For Demo Purposes
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Main Purpose: Interface, Connectivity
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: LatticeECP3 FPGA Device Family
• Primary Attributes: x1/x4 PCI Express Edge Connectors, Both Serial SPI Flash and Parallel Flash
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 7. 100MHz Clock Destinations
SERDES
(see Appendix A, Figure 25)
SERDES/FPGA Reference Clocks
The 50-ohm terminated SMA connectors are optionally provided to supply reference clocks directly to the
LatticeECP3 device. Please contact the factory for information to populate the PCB with SMA connectors.
Table 8. SMA Inputs for External Clock Source
SERDES PCI Express Channels
(see Appendix A, Figure 25)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge-
fingers (CN1 or CN2) that fit directly into a PCI Express host receptacle. Power can be supplied directly from the
PCI Express host via the edge-finger connections.
Table 9. x1 PCI Express Connections
Table 10. x4 PCI Express Connections
PCSA_HDOUTP_0
PCSA_HDOUTN_0
PCSA_HDINP_0
PCSA_HDINN_0
PCSA_REFCLKP
PCSA_REFCLKN
PCIE_PERSETN
PCSB_HDOUTP_0
PCSB_HDOUTN_0
PCSB_HDINP_0
PCSB_HDINN_0
PCSB_HDOUTP_1
PCSB_HDOUTN_1
PCSB_HDINP_1
PCSB_HDINN_1
CML Pin Name
CML Pin Name
FPGA Pin
FPGA Pin
Connector
AD21
AD20
AD13
AD12
AD10
AD11
AF21
AF20
AC17
AC18
AF13
AF12
AF10
AF11
Clock Destination
U20
J6
J7
CPLD
FPGA
FPGA
FPGA
PCIe_CLKp
PCIe_CLKn
PERSTN
PERp0
PERn0
PERp0
PERn0
PERp1
PERn1
PETp0
PETn0
PETp0
PETn0
PETp1
PETn1
PCIE
PCIE
LatticeECP3 PCI Express Solutions Board – Revision A
FPGA_SMA_REFCLKP
FPGA_SMA_REFCLKN
PCB Designation
PCI Express Edge
PCI Express Edge
SERDES Signal
U12
U1
U1
U1
16
A16
A17
B14
B15
A13
A14
A11
A16
A17
B14
B15
A21
A22
B19
B20
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
Integrated endpoint block differential clock pair
Fundamental PCI Express reset
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
K3-LLUM0-GDLLT_IN
Destination Pin
P21-PCLKT2_0
M4-PCLKT7_0
A8
FPGA Pin
W19
V20
Description
Description
User’s Guide