LFE3-95EA-PCIE-DKN Lattice, LFE3-95EA-PCIE-DKN Datasheet - Page 17

• Manufacturer Part Number: LFE3-95EA-PCIE-DKN
• Description: MCU, MPU & DSP Development Tools LatticeECP3-95EA PCI Express Dev Kit
• Manufacturer: Lattice
• Series: ECP3r

Specifications of LFE3-95EA-PCIE-DKN

• Silicon Manufacturer: Lattice Semiconductor
• Silicon Family Name: LatticeECP3
• Kit Contents: Board
• Features: On-board Boot Flash, Switches, LEDs, Displays For Demo Purposes
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Main Purpose: Interface, Connectivity
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: LatticeECP3 FPGA Device Family
• Primary Attributes: x1/x4 PCI Express Edge Connectors, Both Serial SPI Flash and Parallel Flash
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 10. x4 PCI Express Connections (Continued)
FPGA Test Pins
(see Appendix A, Figure 27)
General Purpose DIP Switch
(see Appendix A, Figure 27, SW5)
General-purpose FPGA pins are available for user applications. FPGA pins are connected to a switch (SW5) which
is an SPST side actuated DIP switch. The switch is physically located on the secondary side of the PCB along the
back-panel edge. The switches are connected to a logic level 0 when depressed toward the board and a 1 when
away from the board. The designated pins are connected according to Table 11.
Table 11. FPGA Test Pins (See Appendix A, Figure 26)
PCSB_HDOUTP_2
PCSB_HDOUTN_2
PCSB_HDINP_2
PCSB_HDINN_2
PCSB_HDOUTP_3
PCSB_HDOUTN_3
PCSB_HDINP_3
PCSB_HDINN_3
PCSB_REFCLKP
PCSB_REFCLKN
PCIE_PERSETN
CML Pin Name
FPGA BGA
G8
D9
A6
A5
E9
E8
A7
F9
FPGA Pin
AC10
AD9
AD8
AD6
AD7
AC9
AF9
AF8
AF6
AF7
U20
SW5 Switch Position
PCIe_CLKp
PCIe_CLKn
PERSTN
PERp2
PERn2
PERp3
PERn3
PETp2
PETn2
PETp3
PETn3
PCIE
1
2
3
4
5
6
7
8
LatticeECP3 PCI Express Solutions Board – Revision A
PCI Express Edge
17
A25
A26
B23
B24
A29
A30
B27
B28
A13
A14
A11
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
Integrated endpoint block differential clock pair
Fundamental PCI Express reset
Logic 1
Logic 0
1
2
Description
3
4
5
6
7
User’s Guide
8
PCB