LFE3-95E-PCIE-DKN Lattice, LFE3-95E-PCIE-DKN Datasheet - Page 68

MCU, MPU & DSP Development Tools LatticeECP3 PCI Express Dev Kit

LFE3-95E-PCIE-DKN

Manufacturer Part Number
LFE3-95E-PCIE-DKN
Description
MCU, MPU & DSP Development Tools LatticeECP3 PCI Express Dev Kit
Manufacturer
Lattice
Datasheet

Specifications of LFE3-95E-PCIE-DKN

Processor To Be Evaluated
LFE3-95EA-x
Processor Series
LatticeECP3
Interface Type
SPI
Operating Supply Voltage
1.2 V to 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
LatticeECP3 External Switching Characteristics
Lattice Semiconductor
Clocks
Primary Clock
f
t
t
t
f
f
t
t
Edge Clock
f
t
t
f
t
t
Generic SDR
General I/O Pin Parameters Using Dedicated Clock Input Primary Clock Without PLL
t
t
t
t
t
f
t
t
t
t
t
MAX_PRI
W_PRI
SKEW_PRI
SKEW_PRIB
MAX_PRI
MAX_PRI
SKEW_PRI
SKEW_PRIB
MAX_EDGE
W_EDGE
SKEW_EDGE_DQS
MAX_EDGE
W_EDGE
SKEW_EDGE_DQS
CO
SU
H
SU_DEL
H_DEL
MAX_IO
CO
SU
H
SU_DEL
H_DEL
Parameter
Parameter
6
6
Frequency for Primary Clock Tree
Clock Pulse Width for Primary Clock
Primary Clock Skew Within a Device
Primary Clock Skew Within a Bank
Frequency for Primary Clock Tree
Frequency for Primary Clock Tree
Primary Clock Skew Within a Device
Primary Clock Skew Within a Bank
Frequency for Edge Clock
Clock Pulse Width for Edge Clock
Edge Clock Skew Within an Edge of
the Device
Frequency for Edge Clock
Clock Pulse Width for Edge Clock
Edge Clock Skew Within an Edge of
the Device
Clock to Output - PIO Output Register ECP3-150EA
Clock to Data Setup - PIO Input Regis-
ter
Clock to Data Hold - PIO Input Regis-
ter
Clock to Data Setup - PIO Input Regis-
ter with Data Input Delay
Clock to Data Hold - PIO Input Regis-
ter with Input Data Delay
Clock Frequency of I/O and PFU Reg-
ister
Clock to Output - PIO Output Register ECP3-70E/95E
Clock to Data Setup - PIO Input Regis-
ter
Clock to Data Hold - PIO Input Regis-
ter
Clock to Data Setup - PIO Input Regis-
ter with Data Input Delay
Clock to Data Hold - PIO Input Regis-
ter with Input Data Delay
Over Recommended Commercial Operating Conditions
Description
Description
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70E/95E
ECP3-70E/95E
ECP3-70E/95E
ECP3-70E/95E
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70E/95E
ECP3-70E/95E
ECP3-70E/95E
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70E/95E
ECP3-70E/95E
ECP3-70E/95E
ECP3-70E/95E
3-16
Device
Device
Min.
Min.
0.8
0.8
0.9
0.9
0.0
1.6
1.2
0.1
0.0
1.5
1.3
0.0
DC and Switching Characteristics
1, 2
-8
-8
LatticeECP3 Family Data Sheet
Max.
Max.
500
300
250
500
300
250
500
200
500
200
500
4.0
3.9
2
Min.
Min.
0.9
0.9
1.0
1.0
0.0
1.8
1.3
0.1
0.0
1.8
1.5
0.0
-7
-7
Max.
Max.
420
330
280
420
225
420
330
280
420
210
420
4.4
4.3
Min.
Min.
1.0
1.0
1.2
1.2
0.0
2.1
1.5
0.1
-—
0.0
2.0
1.8
0.0
-6
-6
Max.
Max.
375
360
300
375
360
300
375
220
375
250
375
4.8
4.7
Units
Units
MHz
MHz
MHz
MHz
MHz
ns
ps
ps
ns
ps
ps
ns
ps
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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