LFE3-95E-PCIE-DKN Lattice, LFE3-95E-PCIE-DKN Datasheet - Page 97

• Manufacturer Part Number: LFE3-95E-PCIE-DKN
• Description: MCU, MPU & DSP Development Tools LatticeECP3 PCI Express Dev Kit
• Manufacturer: Lattice

Specifications of LFE3-95E-PCIE-DKN

• Processor To Be Evaluated: LFE3-95EA-x
• Processor Series: LatticeECP3
• Interface Type: SPI
• Operating Supply Voltage: 1.2 V to 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing
Characteristics
AC and DC Characteristics
Table 3-19. Transmit
Table 3-20. Receive
Table 3-21. Reference Clock
BR
T
T
T
T
T
T
Notes:
1. Timing jitter is measured in accordance with SMPTE RP 184-1996, SMPTE RP 192-1996 and the applicable serial data transmission stan-
2. Jitter is defined in accordance with SMPTE RP1 184-1996 as: jitter at an equipment output in the absence of input jitter.
3. All Tx jitter is measured at the output of an industry standard cable driver; connection to the cable driver is via a 50 ohm impedance differen-
4. The cable driver drives: RL=75 ohm, AC-coupled at 270, 1485, or 2970 Mbps, RREFLVL=RREFPRE=4.75kohm 1%.
BR
CID
F
DC
JALIGNMENT
JALIGNMENT
JALIGNMENT
JTIMING
JTIMING
JTIMING
VCLK
Symbol
dard, SMPTE 259M-1997 or SMPTE 292M (proposed). A color bar test pattern is used.The value of f
SMPTE 259M, 540 MHz for SMPTE 344M or 1485 MHz for SMPTE 292M serial data rates. See the Timing Jitter Bandpass section.
tial signal from the Lattice SERDES device.
SDO
SDI
V
Symbol
Symbol
Serial input data rate
Stream of non-transitions
(=Consecutive Identical Digits)
1, 2
2
2
Serial data rate
Serial output jitter, alignment
Serial output jitter, alignment
Serial output jitter, alignment
Serial output jitter, timing
Serial output jitter, timing
Serial output jitter, timing
Video output clock frequency
Duty cycle, video clock
Description
Description
Description
270 Mbps
1485 Mbps
2970Mbps
270 Mbps
1485 Mbps
2970 Mbps
Test Conditions
Test Conditions
Test Conditions
3-45
7(3G)/26(SMPTE
@ 10-12 BER
Triple rates)
DC and Switching Characteristics
Min.
Min.
270
270
—
—
—
—
—
—
LatticeECP3 Family Data Sheet
Min.
27
45
SCLK
Typ.
—
—
—
—
—
—
—
Typ.
50
—
Typ.
is 270 MHz or 360 MHz for
—
—
Max.
2975
0.20
0.20
0.30
0.20
74.25
Max.
1.0
2.0
55
Max.
2970
—
Units
Units
Mbps
MHz
Units
Mbps
UI
UI
UI
UI
UI
UI
%
Bits