Core1553B Eval Board Actel, Core1553B Eval Board Datasheet

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Core1553B Eval Board

Manufacturer Part Number
Core1553B Eval Board
Description
MCU, MPU & DSP Development Tools Bus Controller
Manufacturer
Actel
Datasheet

Specifications of Core1553B Eval Board

Processor To Be Evaluated
A54SX32A-BG329
Interface Type
RS-232
Core1553BBC MIL-STD-1553B Bus Controller
Product Summary
Intended Use
Key Features
Supported Families
Core Deliverables
© 2005 Actel Corporation
December 2005
• 1553B Bus Controller (BC)
• DMA Backend Interface to External Memory
• Supports MIL-STD-1553B
• Interfaces to External RAM
• Selectable Clock Rate of 12, 16, 20, or 24 MHz
• Provides Direct CPU Access to Memory
• Interfaces to Standard 1553B Transceivers
• Fully Automated Message Scheduling
• Fusion
• ProASIC3/E
• ProASIC
• Axcelerator
• RTAX
• SX-A
• RTSX-S
• Netlist Version
• RTL Version
– Supports up to 128kbytes of Memory
– Synchronous
– Backend Interface Identical to Core1553BRT
– Frame Support
– Conditional Branching and Sub-routines
– Variable Inter-message Gaps and RT Response
– Real Time Clock for Message Scheduling
– Asynchronous Message Support
– Compiled RTL Simulation Model, Compliant
– Compatible with the Actel Designer Place-and-
– VHDL or Verilog Core Source Code
Interface
Times
with the Actel Libero™ Integrated Design
Environment (IDE)
Route Tool
PLUS
or
Asynchronous
Backend
v 4 .0
Synthesis and Simulation Support
Verification and Compliance
Development System (Optional)
Contents
General Description ................................................... 2
Core1553BBC Device Requirements .......................... 4
Core1553BBC Verification and Compliance .............. 4
MIL-STD-1553B Bus Overview .................................... 4
I/O Signal Descriptions ............................................. 6
Bus Transceivers ........................................................ 20
Development System ............................................... 20
Typical BC System ..................................................... 22
Specifications ............................................................ 24
Ordering Information .............................................. 28
List of Changes ......................................................... 29
Datasheet Categories ............................................... 29
• Actel-Developed Testbenches, VHDL and Verilog
• Synthesis: Synplicity
• Simulation: Vital-Compliant VHDL Simulators and
• Actel-Developed Simulation Testbench
• Core Implemented on the 1553B BC Development
• Third-Party 1553B Compliance Testing of the
• Complete 1553B BC Implementation in an SX-A
• Includes a PCI Interface for Host CPU Connection
• Includes
– Synthesis Scripts
FPGA Compiler
OVI-Compliant Verilog Simulators
System
1553B Encoder and Decoder Blocks Implemented
in an A54SXA32-STD Device
Device
Components
Transceivers
TM
/FPGA Express
®
, Synopsys
and
TM
®
(Design Compiler
Bus
), Exemplar
Termination
TM
®
1
/

Related parts for Core1553B Eval Board

Core1553B Eval Board Summary of contents

Page 1

... Core Deliverables • Netlist Version – Compiled RTL Simulation Model, Compliant with the Actel Libero™ Integrated Design Environment (IDE) – Compatible with the Actel Designer Place-and- Route Tool • RTL Version – VHDL or Verilog Core Source Code December 2005 © 2005 Actel Corporation – ...

Page 2

... The core consists of five main blocks: the 1553B encoder, the 1553B decoder, a protocol controller block, a CPU interface, and a backend interface BUSAINEN BUSAINP BUSAINN BUSAOUTINH BUSAOUTP BUSAOUTN BUSBINEN BUSBINP BUSBIN BUSAOUTINH BUSBOUTP BUSBOUTN Core1553BBC Actel FPGA Encoder Protocol Controller Decoder Backend Interface CPU Interface and Registers Core1553BBC v4.0 (Figure 2). RCVSTBA ...

Page 3

A single 1553B encoder takes each word to be transmitted and serializes it using Manchester encoding. The encoder includes independent logic to prevent the BC from transmitting for greater than the allowed period and to provide loopback fail logic. The ...

Page 4

... Axcelerator RTAX-S SX-A RTSX-S The Core1553BBC clock rate can be programmed to 12, 16, 20 MHz. All Actel device families listed in Table 1 easily meet this performance requirement. When implemented in ProASIC devices, the Core1553BBC can connect directly to the internal FPGA memory blocks, eliminating the need for external memories ...

Page 5

Message Types The 1553B bus supports ten message transfer types, allowing basic point-to-point and broadcast data transfers, mode code messages, and direct RT-to-RT messages. BC-to-RT Transfer BC Transmit Data Data Command RT-to-BC Transfer ...

Page 6

Core1553BBC MIL-STD-1553B Bus Controller Word Formats There are only three types of words in a 1553B message: a command word (CW), a data word (DW), and a status word (SW). Each 20-bit word consists of a 3-bit sync pattern, 16 ...

Page 7

Table 3 • Control and Status Signals Name Type Description CLK In Master clock input (either 12 MHz, 16 MHz, 20 MHz MHz) RSTINn In Reset input (active low) INTOUT Out Interrupt Request (active high). The CPU is ...

Page 8

Core1553BBC MIL-STD-1553B Bus Controller Backend Interface The backend interface supports both synchronous operation and asynchronous operation to backend devices. Synchronous operation directly supports the use of internal FPGA memory blocks. Asynchronous operation allows connection to standard external memory devices. Table ...

Page 9

Miscellaneous I/O Several inputs are used to modify the core functionality to simplify integration in the application. These inputs should be tied to logic '0' or logic '1' as appropriate Table 6 • Memory Access Requirements CPUMEMEN CLK Speed MHz ...

Page 10

Core1553BBC MIL-STD-1553B Bus Controller Table 8 • Bus Controller Registers Address Name Type 110 STACKPTR RW 111 INTERRUPT RW Table 9 • Setup Register Bits Name Type Reset 15 FORCEORUN RW 14 CLOCKEN RW 13:12 CLKFREQ RW 11 RETRYMODE WR ...

Page 11

Table 9 • Setup Register (Continued) Bits Name Type Reset 3:2 RESPTIME RW 1:0 Reserved R Table 10 • Control Register Bits Name Type Function 3 ASYNC W Writing a '1' causes the bus controller to jump to process the ...

Page 12

Core1553BBC MIL-STD-1553B Bus Controller Table 12 • Interrupt Register Bits Name Type Function 15 INTPENDING RW When set, the BC has an interrupt pending. This bit is set if any of the INTVECT bits are set. 14:8 INTVECT RW Interrupt ...

Page 13

Bus Controller Operation After power-up, the bus controller waits while the CPU sets up the bus controller memory and registers. The memory contains an instruction list, message blocks, and data blocks. Once the instruction list, message blocks, and data blocks ...

Page 14

Core1553BBC MIL-STD-1553B Bus Controller Table 14 • Supported Instructions (Continued) OPCODE Function Condition Code Parameter 0110 LOADC Yes 0111 WAITC Yes 1000 CALL Yes 1001 RET Yes 1010 RETAS Yes 1011 STOREF Yes Others Illegal N/A Table 15 • Condition ...

Page 15

Table 15 • Condition Codes (Continued) Condition Code Function Description 10111 NBR Performs the instruction if the Broadcast Received bit was not set in the last received status word 11000 NSR Performs the instruction if the Service Request bit was ...

Page 16

Core1553BBC MIL-STD-1553B Bus Controller Message Block An 8-word message block controls each message. The BC reads the 1553B command words from the message block and will write the received status words back to message block. Message blocks must be positioned ...

Page 17

Table 16 • Message Block (Continued) Offset Contents Written by Description 6 TSW BC 7 Reserved – Message Transfer Status Word. Provides status information on the message block. The CPU should clear this field when setting up the message block ...

Page 18

Core1553BBC MIL-STD-1553B Bus Controller Detailed Operation Flow Table 17 shows the operations the core goes through in processing a message list containing two messages. The first message is a BC-to-RT transfer of three words, and the second is an RT-to-BC ...

Page 19

Error Conditions Core1553BBC monitors bus errors and in most cases will perform automatic retry operations if recovery is possible (Table 18). Table 18 • Error Conditions Error Condition Group Error Signaling 1553B signaling error, parity, Manchester error, too many or ...

Page 20

... A complete 1553B Bus controller development system is also available. The Actel part number is “Core1553BBC Eval Board." The development system implements a PCI to 1553B bus controller on a single PCB using an Actel A54SX32A FPGA. The PCI target interface uses the Actel CorePCI66 PCI target interface core. ...

Page 21

... Memory 64K*16 PCI Interface Development PCB Figure 7 • Core1553BBC Development System Core1553BBC MIL-STD-1553B Bus Controller Memory Access PCI Target Interface Core1553BBC Actel FPGA v4.0 Pulse Transformer Pulse Transceiver Transformer 21 ...

Page 22

... BUSAINEN RCVSTBA BUSAINP RXDAIN BUSAINN RXDAIN BUSAOUTINH TXINHA BUSAOUTP TXDAIN BUSAOUTN TXDAIN BUSBINEN RCVSTBA BUSBINP RXDBIN BUSBIN RXDBIN BUSAOUTINH TXINHA BUSBOUTP TXDBIN BUSBOUTN TXDBIN Core1553BBC Actel FPGA v4.0 Figure 9 on page 23. In this case, both the Pulse Transformer Transceiver Pulse Transformer ...

Page 23

... Figure 9 • Core1553BBC Using Shared Memory Core1553BBC MIL-STD-1553B Bus Controller BUSAINEN RCVSTBA BUSAINP RXDAIN BUSAINN RXDAIN BUSAOUTINH TXINHA BUSAOUTP TXDAIN BUSAOUTN TXDAIN Transceiver BUSBINEN RCVSTBA BUSBINP RXDBIN BUSBIN RXDBIN BUSAOUTINH TXINHA BUSBOUTP TXDBIN BUSBOUTN TXDBIN Core1553BBC Actel FPGA v4.0 Pulse Transformer Pulse Transformer 23 ...

Page 24

Core1553BBC MIL-STD-1553B Bus Controller Specifications CPU Interface Timing CPUCSN CPURDN CPUADDR CPUMEM CPUDOUT CPUDEN CPUWAITN Figure 10 • CPU Interface Register Read Cycle CLK CPUCSN CPUWRN[1:0] CPUADDR CPUMEM CPUDIN CPUWAITN Figure 11 • CPU Interface Register Write Cycle CLK CPUCSN ...

Page 25

CLK CPUCSN CPUWRN CPUADDR CPUMEM CPUDIN CPUWAITN Figure 13 • CPU Interface Memory Write Cycle CPUWAITn will be driven low for a minimum of three (3) clock cycles for write cycles, four (4) for read cycles, and the number of ...

Page 26

Core1553BBC MIL-STD-1553B Bus Controller CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR MEMDOUT MEMWRn MEMWAITn Figure 16 • Asynchronous Memory Write Cycle CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn MEMADDR MEMDIN MEMWAITn Figure 17 • Synchronous Memory Read Cycle CLK MEMREQn ...

Page 27

CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn MEMADDR MEMDIN MEMWAITn Figure 19 • Synchronous Memory Read Cycle with MEMGNTn Active CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR MEMDOUT MEMWRn MEMWAITn Figure 20 • Synchronous Memory Write Cycle with MEMGNTn Active ...

Page 28

... To meet the 1553B transmission bit rate requirements, the Core1553BBC clock input must be 12, 16, 20 MHz with a tolerance of ±0.01%. Ordering Information Core1553BBC can be ordered through your local Actel sales representative. It should be ordered using the following number scheme: Core1553BBC-XX, where XX is Table 19 • Ordering Codes ...

Page 29

List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version ( v3.0 The "Supported Families" section Table 1 was updated to include ...

Page 30

... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court Dunlop House, Riverside Way Mountain View, CA Camberley, Surrey GU15 3YL 94043-4655 USA United Kingdom Phone 650.318.4200 Phone +44 (0) 1276 401 450 Fax 650 ...

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