CorePCI Eval Board Actel, CorePCI Eval Board Datasheet
CorePCI Eval Board
Specifications of CorePCI Eval Board
Related parts for CorePCI Eval Board
CorePCI Eval Board Summary of contents
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... SX-A 1 • RTSX-S Design Source Provided • VHDL and Verilog-HDL Design Source • Actel-Developed Testbench October 2004 © 2004 Actel Corporation Synthesis and Simulation Support • Synthesis: Exemplar and Synplicity • Simulation: Vital-Compliant VHDL Simulators and OVI- Compliant Verilog Simulators and ...
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... Target controller through a generic interface. The wrapper combines the Target and Master blocks with the backend for implementation in a single Actel device. CorePCI can be customized in two different ways. First, a variety of variables are provided to easily change parameters such as memory and I/O sizes. The second method is to develop user-specific backend controllers for non-standard peripherals ...
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CorePCI Device Requirements Performance requirements and bus size both drive device selection. Table 1 summarizes the device requirements. A typical 64-bit PCI system requires at least 200 I/Os. on page 5 shows typical pin counts. The actual number of I/O ...
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CorePCI v5.41 Table 2 • Device Utilization for CorePCI Functions Target Device 32-Bit A54SX16A 54% A54SX16P 54% A54SX32A 27% A54SX72A 13% RT54SX32S 27% RT54SX72S 13% AX125 39% AX250 19% AX500 10% AX1000 4% AX2000 2% RTAX250S 19% RTAX1000S 4% RTAX2000S ...
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Utilization Statistics Utilization statistics are given in Table 3 gives a detailed breakdown of the actual gate counts for each of the core variations and options listed in Table 3. The antifuse column indicates the typical R and C module ...
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CorePCI v5.41 CorePCI IP Functional Block Diagram CorePCI consists of six major functional blocks, shown in Figure 2 on page 7. These blocks are the DMA state machine, the address phase dataphase state machine, the datapath, parity, and the configuration ...
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PCI Bus FRAMEn IRDYn STOPn DEVSELn TRDYn SERRn IDSEL AD PAR CBE PERRn INTAn REQn GNTn DMA Controller CLK RSTn For a complete list of signal descriptions, refer to Figure 2 • CorePCI Block Diagram Dataphase Address Phase State Machine ...
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CorePCI v5.41 Table 5 • CorePCI Interface Signals * Name Type Description CLK Input 33 MHz or 66 MHz clock input for the PCI core RSTn Input Active LOW asynchronous reset AD Bidirectional Multiplexed 32-bit or 64-bit address and data ...
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Table 6 • CorePCI Backend Interface Signal 1,2 Name Type CLK_OUT Output BAR0_MEM_CYC Output BAR1_CYC Output CONFIG_CYC Output RD_CYC Output WR_CYC Output MEM_DIN Input MEM_DOUT Output MEM_DATA_DEN Output MEM_DATA_DEN64 Output 3 MEM_ADD[N:0] Output DP_START Output DP_START64 DP_DONE Output RD_BE_NOW Output ...
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CorePCI v5.41 Table 6 • CorePCI Backend Interface Signal (Continued) 1,2 Name Type WR_BE_NOW[3:0] Output WR_BE_NOW64[3:0] WR_BE_RDY Input PIPE_FULL_CNT[2:0] Input BE_REQ Input BE_GNT Output DMA_GNT Output BUSY_MASTER Input STALL_MASTER Input ERROR Input Notes: 1. Active LOW signals are designated with ...
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Table 6 • CorePCI Backend Interface Signal (Continued) 1,2 Name Type BUSY Input EXT_INTn Input CS_CONTROLn Input RD_CONTROLn Input WR_CONTROLn Input CONTROL_ADD[1:0] Input MASTER_BE[3:0] Input MASTER_BE64[3:0] Input Notes: 1. Active LOW signals are designated with a trailing lower-case n. 2. ...
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CorePCI v5.41 CorePCI Target Function CorePCI Target function acts like a slave on the PCI bus. The Target controller monitors the bus and checks for hits to either configuration space or to the address space defined in its base address ...
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Read-Only Configuration Registers The read-only registers listed in Table 8 on page 13 default values, but should be modified by the designer. See the PCI specification for setting these values: • Vendor ID • Device ID • Revision ID • ...
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CorePCI v5.41 Table 9 • Command Register (04h) Bit Type Description 0 RW I/O Space A value of '0' disables the device’s response to I/O space addresses. Set to '0' after reset Memory Space A value of '0' ...
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Table 10 • Status Register (06h) (Continued) Bit Type Description 6 RO UDF Supported Set to '0' – no user definable features Fast Back-to-Back Capable Set to '0' – fast back-to-back to same agent only Data ...
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CorePCI v5.41 Table 11 • Memory Base Address Register Bit Definition (Locations 10h or 14h) Bit Type Description 0 RO Set to '0' to indicate memory space. 2–1 RO Set to '00' to indicate mapping into any 32-bit address space. ...
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CorePCI Master Function The Master function in CorePCI is designed to perform the following: • Arbitrate for the PCI bus • Initiate an access by asserting FRAMEn and providing the address and command • Pass dataflow control to the Target ...
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CorePCI v5.41 Table 20 • DMA Control Register Bit Type Description 0–1 RW DMA Error 00 – No Error 01 – Master Abort 10 – Parity Error 11 – Target Abort 2 RO DMA Done A '1' indicates that the ...
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Table 20 • DMA Control Register (Continued) Bit Type Description 28 RO Reserved (set to '0'). 31–29 RW Maximum Burst Length When set to '000'b, the Master controller will attempt to complete the requested transfer in a single burst. When ...
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CorePCI v5.41 Table 22 • CorePCI Customization Constants Constant Type 1 USER_DEVICE_ID Binary 1 USER_VENDOR_ID Binary 1 USER_REVISION_ID Binary 1 USER_BASE_CLASS Binary 1 USER_SUB_CLASS Binary 1 USER_PROGRAM_IF Binary 1 USER_SUBSYSTEM_ID Binary 1 USER_SUBVENDOR_ID Binary BIT_64 Binary 1 MHZ_66 Binary 1 ...
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Table 22 • CorePCI Customization Constants (Continued) Constant Type ENABLE_BAR_OVERFLOW Binary EXPORT_CLOCK_OUT Binary Notes: 1. Not applicable in Target-only core. 2. Only applicable in Target+DMA core. 3. Not applicable in Master-only core. Description When ENABLE_BAR_OVERFLOW is set the core will ...
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CorePCI v5.41 System Timing To meet 33 MHz PCI timing specifications, only standard speed devices from the A54SX, A54SX-A, AX, A500K, and the APA families are required. To meet 66 MHz PCI timing requirements, the "–3" speed grade parts from ...
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CLK FRAMEn AD PAR CBE IRDYn TRDYn STOPn DEVSELn IDSEL Notes the Target’s IDSEL is asserted when FRAMEn is asserted and the command bus is '1011', then a configuration write cycle is indicated. 2. The Target claims the ...
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CorePCI v5.41 In the case of a PCI read, the backend must prefetch the memory data in order to ensure continuity on long bursts. If prefetching causes a problem, for example in a FIFO, the backend logic should shadow the ...
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CLK FRAMEn AD PAR CBE IRDYn TRDYn STOPn DEVSELn DP_START BARn_CYC RD_CYC DP_DONE RD_BE_RDY RD_BE_NOW MEM_ADDRESS MEM_DATA Notes: 1. When FRAMEn is asserted and the command bus is '0110', then a read from memory space is indicated. 2. The Target ...
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CorePCI v5.41 CLK FRAMEn REQ64n AD[63:32] AD[31:0] PAR PAR64 CBE IRDYn TRDYn STOPn DEVSELn ACK64n DP_START DP_START64 DP_DONE WR_BE_RDY WR_BE_NOW WR_BE_NOW64 MEM_ADDRESS MEM_DATA[63:32] MEM_DATA[31:0] Notes: 1. When FRAMEn and REQ64n is asserted and the command bus is '0111', then a ...
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CLK FRAMEn REQ64n AD[63:32] AD[31:0] PAR PAR64 CBE IRDYn TRDYn STOPn DEVSELn ACK64n DP_START DP_START64 DP_DONE RD_BE_RDY RD_BE_NOW RD_BE_NOW64 MEM_ADDRESS MEM_DATA[63:32] MEM_DATA[31:0] Notes: 1. When FRAMEn and REQ64n is asserted and the command bus is '0110', then a 64-bit read ...
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CorePCI v5.41 Paced Transactions Backend throttle transfers provide mechanism for supporting slow response devices. The backend transactions are paced using the RD_BE_RDY and WR_BE_RDY signals. These signals can be used to pace either single DWORD or burst transactions. CLK FRAMEn ...
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CLK FRAMEn AD[31:0] PAR CBE[3:0] 0110 IRDYn TRDYn STOPn DEVSELn DP_START DP_DONE RD_BE_RDY RD_BE_NOW MEM_ADDRESS[23:2] MEM_DATA[31:0] Notes: 1. The RD_BE_RDY can be asserted one cycle before the backend is ready to transmit data. 2. The RD_BE_RDY signal is asserted ...
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CorePCI v5.41 CLK 1 2 FRAMEn AD[31:0] data2 data3 data4 Pd1 Pd2 PAR CBE[3:0] IRDYn TRDYn STOPn DEVSELn DP_START DP_DONE WR_BE_RDY WR_BE_NOW MEM_ADDRESS[23:2] add1 add2 MEM_DATA[31:0] data1 data2 data3 Notes the example, the flow of data is interrupted ...
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CLK 1 2 FRAMEn AD[31:0] data2 data3 Pd1 Pd2 PAR CBE[3:0] IRDYn TRDYn STOPn DEVSELn DP_START DP_DONE RD_BE_RDY RD_BE_NOW MEM_ADDRESS[23:2] add3 add4 MEM_DATA[31:0] data3 data4 Notes the example, the PCI Master interrupts the flow of data by de-asserting ...
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CorePCI v5.41 1 CLK FRAMEn AD PAR CBE IRDYn TRDYn STOPn DEVSELn DP_START DP_DONE RD_BE_RDY RD_BE_NOW PIPE_FULL_CNT MEM_ADDRESS MEM_DATA Figure 15 • Backend Latency Read Transaction Target Abort The backend may cause a target abort abort, which is defined by ...
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Target Retry and Disconnect When the backend is busy or unable to provide the data requested, the Target controller will respond with either a retry or a disconnect cycle. If the backend has arbitrated for control of the backend bus ...
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CorePCI v5.41 CLK FRAMEn AD[31:0] PAR CBE[3:0] IRDYn TRDYn STOPn DEVSELn BUSY DP_START DP_DONE RD_BE_RDY RD_BE_NOW MEM_ADDRESS[23:2] MEM_DATA[31:0] Notes: 1. During a normal PCI transaction, the backend reaches a point where it is unable to deliver data and de-asserts RD_BE_RDY. ...
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CLK 1 2 EXT_INTn INTAn Notes: 1. The EXT_INTn signal is sampled on the rising edge of each clock the EXT_INTn signal is asserted and sampled in cycle 2, then the PCI INTAn signal will be asserted in ...
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CorePCI v5.41 CLK 1 DP_START FRAMEn AD[31:0] PAR C_BE[3:0] IRDYn TRDYn STOPn DEVSELn DP_DONE BARn_CYC WR_CYC MEM_ADDRESS[23:2] MEM_DATA[31:0] WR_BE_RDY WR_BE_NOW[3:0] Notes: 1. Once CorePCI is granted the PCI bus, the core asserts DP_START and begins the process of enabling the ...
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CLK 1 2 DP_START FRAMEn AD[31:0] PAR C_BE[3:0] IRDYn TRDYn STOPn DEVSELn DP_DONE BARn_CYC RD_CYC MEM_ADDRESS[23:2] MEM_DATA[31:0] RD_BE_RDY RD_BE_NOW Notes: 1. Once CorePCI is granted the PCI bus, the core asserts DP_START and begins the process of enabling the bus ...
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CorePCI v5.41 Backend Control of DMA Activity The core provides two signals, BUSY_MASTER and STALL_MASTER, that can be used to control the DMA transfers. BUSY_MASTER allows a DMA transfer to be stopped, and STALL_MASTER allows for slow backends to meet ...
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CLK DP_START STALL_MASTER BUSY_MASTER FRAMEn AD[31:0] CBE[3:0] IRDYN TRDYn STOPn DEVSELn DP_DONE RD_CYC MEM_ADDRESS[23:2] MEM_DATA[31:0] RD_BE_RDY RD_BE_NOW Figure 24 • DMA Master with STALL_MASTER Asserted When STALL_MASTER is active (see possible for the PCI GNT to go away; in this ...
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... CorePCI v5.41 Ordering Information CorePCI v5.41 can be ordered through your local Actel sales representative. It should be ordered using the following numbering scheme; CorePCI-XX where XX corresponds to one of the variables in Table 23 • Ordering Codes XX Description EV Evaluation Version SN Netlist for single-use on Actel devices AN Netlist for unlimited use on Actel devices ...
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List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version ( v4.0 ProASIC3/E data was added. Datasheet Categories In order to provide the ...
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