A3PE-BRD600-SKT Actel, A3PE-BRD600-SKT Datasheet - Page 17

• Manufacturer Part Number: A3PE-BRD600-SKT
• Description: MCU, MPU & DSP Development Tools ProASIC3/E Starter Kit
• Manufacturer: Actel

Specifications of A3PE-BRD600-SKT

• Processor To Be Evaluated: ProASIC3/E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Circuits
40 MHz Oscillator
LED Device Connections
ProASIC3/E Starter Kit User’s Guide and Tutorial
The board is fabricated with 6 layers of copper. The layers are arranged as follows from the top of the board down to the
bottom:
Note:
Refer to the diagrams in
The ProASIC3/E Evaluation Board has two clock circuits: a 40 MHz oscillator and a manual clock.
The 40 MHz oscillator on the board is a 10 ppm stability crystal module which will give good LVDS performance.
Should better stability be required, an external oscillator may be provided via the SMA connector. Typically a TCXO
will give 1 ppm stability and an OCXO will give 0.1 ppm stability. Both the default on-board oscillator and the SMA are
connected to the CLK F input of the West bank of the FPGA. Position is also provided on the board for mounting a
second crystal oscillator module connected to the CLK C input of the FPGA on the East bank.
Eight LEDs are connected to the device via jumpers. If the jumpers are in place, the device I/O can drive the LEDs. The
LEDs change based on the following output:
• A ‘1’ on the output of the device lights the LED.
• A ‘0’ on the output of the device switches off the LED.
• An unprogrammed or tristated output may show a faintly lit LED.
Note:
Table 2-1 on page 18
Layer 1 – Top signal layer
Layer 2 – Ground Plane
Layer 3 – Signal layer 3, used for LVDS receive and other signals
Layer 4 – Signal layer 4, used for LVDS transmit and other signals
Layer 5 – Power Plane
Layer 6 – Bottom signal layer
It will be noted for signal integrity that the two LVDS layers are sandwiched between ground and power planes
to isolate them as best as possible from external influences.
If the I/O voltage of Bank 5 (on A3PE, set by SW8) or Bank 2 (A3P, set by SW8 and SW7 being at the same
level) is not at least 2.5 V, the LEDs will not illuminate. A setting of 1.8 V on the voltage bank will cause extremely
faint illumination.
lists the LED/device connections.
“Signal Layers” on page
93.
Clock Circuits
17