A3PE-BRD600-SKT Actel, A3PE-BRD600-SKT Datasheet - Page 51

• Manufacturer Part Number: A3PE-BRD600-SKT
• Description: MCU, MPU & DSP Development Tools ProASIC3/E Starter Kit
• Manufacturer: Actel

Specifications of A3PE-BRD600-SKT

• Processor To Be Evaluated: ProASIC3/E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Step 4 – Perform Post-Synthesis Simulation
ProASIC3/E Starter Kit User’s Guide and Tutorial
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The next step is simulating the VHDL netlist of the design using the VHDL testbench created in the section,
a stimulus file and generate a VHDL testbench:” on page
1.
Set the following in the dialog box:
Technology: Actel ProASIC3E (set by Libero IDE)
Part: A3PE600
Fan-out Guide: 12 (default)
Hard Limit to Fan-out: Off (default). This refers to the fan-out limit.
Accept the default values for each of the other tabs in the Options for Implementation dialog box and click OK.
Set the following in the dialog box:
Technology: Actel ProASIC3 (set by Libero IDE)
Part: A3P250
Fan-out Guide: 12 (default)
Hard Limit to Fan-out: Off (default). This refers to the fan-out limit.
Accept the default values for each of the other tabs in the Options for Implementation dialog box and click OK.
In the Synplify main window, click Run. Synplify compiles and synthesizes the design into a netlist called Top.edn.
The resulting Top.edn file is then automatically translated by Libero IDE into a VHDL netlist called Top.vhd.
The resulting EDIF and VHDL files are displayed under Implementation Files in the File Manager.
If any errors appear after you click the Run button, edit the file using the Synplify editor. To edit the file, double-
click the file name in the Synplify window. Any changes made here are saved to the original design file in Libero
IDE.
Save and close Synplify. From the File menu, click Exit to close Synplify. Click Yes to save any settings made to the
Top_syn.prj in Synplify.
Click the Simulation icon in the Libero IDE Design Flow window, or right-click the Top.vhd file in the Design
Hierarchy tab and select Run Post-Synthesis Simulation. This launches the ModelSim Simulator that compiles the
source file and testbench.
Figure 7-27. Options for Implementation Dialog Box-A3P250
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Step 4 – Perform Post-Synthesis Simulation
“To create
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