PDTC115EM T/R NXP Semiconductors, PDTC115EM T/R Datasheet - Page 9

Digital Transistors TRANS RET TAPE-7

PDTC115EM T/R

Manufacturer Part Number
PDTC115EM T/R
Description
Digital Transistors TRANS RET TAPE-7
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PDTC115EM T/R

Configuration
Single
Transistor Polarity
NPN
Typical Input Resistor
100 KOhms
Typical Resistor Ratio
1
Mounting Style
SMD/SMT
Package / Case
SOT-883-3
Collector- Emitter Voltage Vceo Max
50 V
Peak Dc Collector Current
20 mA
Maximum Operating Temperature
+ 150 C
Minimum Operating Temperature
- 65 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PDTC115EM,315
NXP Semiconductors
2004 Aug 06
NPN resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩ
Plastic single-ended leaded (through hole) package; 3 leads
DIMENSIONS (mm are the original dimensions)
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
UNIT
mm
VERSION
OUTLINE
SOT54
D
5.2
5.0
A
0.48
0.40
d
b
E
3
1
2
0.66
0.55
b 1
IEC
b
1
0.45
0.38
c
4.8
4.4
D
JEDEC
TO-92
1.7
1.4
d
REFERENCES
0
4.2
3.6
E
2.54
A
e
SC-43A
JEITA
scale
2.5
9
1.27
e 1
14.5
12.7
5 mm
L
L 1
L
max.
2.5
1
(1)
L
PROJECTION
EUROPEAN
PDTC115E series
Product data sheet
ISSUE DATE
b
04-06-28
04-11-16
c
e 1
e
SOT54

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