ADF4350BCPZ Analog Devices Inc, ADF4350BCPZ Datasheet

F-N With High Performance Integrated VCO

ADF4350BCPZ

Manufacturer Part Number
ADF4350BCPZ
Description
F-N With High Performance Integrated VCO
Manufacturer
Analog Devices Inc
Type
Fanout Distribution, Fractional N, Integer N, Clock/Frequency Synthesizer (RF)r
Datasheet

Specifications of ADF4350BCPZ

Design Resources
Broadband Low EVM Direct Conversion Transmitter (CN0134) Broadband Low EVM Direct Conversion Transmitter Using LO Divide-by-2 Modulator (CN0144) Using low noise linear drop-out regulators to power wideband PLL & VCO IC's (CN0147)
Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:3
Differential - Input:output
No/No
Frequency - Max
4.4GHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LFCSP
Frequency-max
4.4GHz
Frequency
4.4GHz
Supply Voltage Range
3V To 3.6V
Digital Ic Case Style
LFCSP
No. Of Pins
32
Operating Temperature Range
-40°C To +85°C
Clock External Input
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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FEATURES
Output frequency range: 137.5 MHz to 4400 MHz
Fractional-N synthesizer and integer-N synthesizer
Low phase noise VCO
Programmable divide-by-1/-2/-4/-8/-16 output
Typical rms jitter: 0.5 ps rms
Power supply: 3.0 V to 3.6 V
Logic compatibility: 1.8 V
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast-lock mode
Cycle slip reduction
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX,
Test equipment
Wireless LANs, CATV equipment
Clock generation
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
GSM, PCS, DCS, DECT)
REF
DATA
CLK
LE
IN
DOUBLER
CE
×2
DATA REGISTER
N COUNTER
INTEGER
REG
AGND
SDV
DD
COUNTER
10-BIT R
FRACTION
REG
INTERPOLATOR
THIRD-ORDER
FRACTIONAL
AV
DD
DGND
Wideband Synthesizer with Integrated VCO
MODULUS
DIVIDER
FUNCTIONAL BLOCK DIAGRAM
REG
÷2
FUNCTION
LATCH
DV
DD
CP
GND
Figure 1.
DETECT
LOCK
COMPARATOR
V
PHASE
P
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
GENERAL DESCRIPTION
The ADF4350 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
if used with an external loop filter and external reference
frequency.
The ADF4350 has an integrated voltage controlled oscillator
(VCO) with a fundamental output frequency ranging from
2200 MHz to 4400 MHz. In addition, divide-by-1/2/4/8 or 16
circuits allow the user to generate RF output frequencies as low
as 137.5 MHz. For applications that require isolation, the RF
output stage can be muted. The mute function is both pin- and
software-controllable. An auxiliary RF output is also available,
which can be powered down if not in use.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
MULTIPLEXER
R
MULTIPLEXER
CORE
VCO
CHARGE
SET
PUMP
V
÷1/2/4/8/16
SD
VCO
GND
A
GNDVCO
©2008 Analog Devices, Inc. All rights reserved.
FL
O
SWITCH
ADF4350
OUTPUT
OUTPUT
STAGE
STAGE
ADF4350
www.analog.com
MUXOUT
SW
LD
CP
V
V
V
TEMP
RF
RF
PDB
RF
RF
TUNE
REF
COM
OUT
OUT
OUT
OUT
OUT
RF
A+
A–
B+
B–

Related parts for ADF4350BCPZ

ADF4350BCPZ Summary of contents

Page 1

FEATURES Output frequency range: 137.5 MHz to 4400 MHz Fractional-N synthesizer and integer-N synthesizer Low phase noise VCO Programmable divide-by-1/-2/-4/-8/-16 output Typical rms jitter: 0.5 ps rms Power supply: 3 3.6 V Logic compatibility: 1.8 V Programmable dual-modulus ...

Page 2

ADF4350 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings ............................................................ 6 Transistor Count ........................................................................... 6 ESD ...

Page 3

SPECIFICATIONS SDV = V = 3.3 V ± 10%; AGND = DGND = VCO DD P temperature range is −40°C to +85°C. Table 1. Parameter REF CHARACTERISTICS IN Input ...

Page 4

ADF4350 Parameter NOISE CHARACTERISTICS VCO Phase-Noise Performance 6 7 Normalized In-Band Phase Noise Floor 8 In-Band Phase Noise 9 Integrated RMS Jitter Spurious Signals Due to PFD Frequency Level of Signal With RF Mute Enabled 1 AC coupling ensures AV ...

Page 5

TIMING CHARACTERISTICS SDV = V = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used VCO DD P otherwise noted. Table 2. ...

Page 6

ADF4350 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND GND VCO VCO DD Digital I/O Voltage to GND Analog I/O ...

Page 7

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND. Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK Serial Clock Input. Data is clocked into the 32-bit shift ...

Page 8

ADF4350 Pin No. Mnemonic Description 22 R Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage SET bias at the R 25 where 5.1 kΩ SET ...

Page 9

TYPICAL PERFORMANCE CHARACTERISTICS –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 1k 10k 100k 1M FREQUENCY (Hz) Figure 4. Open-Loop VCO Phase Noise, 2.2 GHz –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 ...

Page 10

ADF4350 0 –20 –40 –60 –80 –100 –120 –140 –160 1k 10k 100k FREQUENCY (Hz) Figure 10. Integer-N Phase Noise and Spur Performance. GSM900 Band 904 MHz, REF = 100 MHz, PFD = 800 kHz, Output Divide-by-4 OUT ...

Page 11

CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 16. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. This ensures ...

Page 12

ADF4350 MUXOUT AND LOCK DETECT The output multiplexer on the ADF4350 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 (for details, see Figure 26). Figure 19 ...

Page 13

The VCO shows variation the V V band and from band-to-band. It has been shown for wideband applications covering a wide frequency range (and changing output dividers) that a value of 33 MHz/V provides the most accurate ...

Page 14

ADF4350 REGISTER MAPS 16-BIT INTEGER VALUE (INT) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 N16 N15 N14 ...

Page 15

INTEGER VALUE (INT) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 0 N16 N15 N14 N13 N12 N11 N10 ...

Page 16

ADF4350 LOW NOISE AND LOW SPUR MUXOUT MODES DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 0 L2 ...

Page 17

RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 D13 D12 ...

Page 18

ADF4350 REGISTER 0 Control Bits With Bits [C3:C1] set Register 0 is programmed. Figure 24 shows the input data format for programming this register. 16-Bit INT Value These sixteen bits set the INT value, which determines ...

Page 19

When the doubler is enabled and the lowest spur mode is chosen, the in-band phase noise performance is sensitive to the REF duty cycle. The phase noise degradation can much for the REF duty ...

Page 20

ADF4350 REGISTER 3 Control Bits With Bits [C3:C1] set Register 3 is programmed. Figure 27 shows the input data format for programming this register. CSR Enable Setting DB18 to 1 enables cycle slip reduction. This is ...

Page 21

INITIALIZATION SEQUENCE The following sequence of registers is the correct sequence for initial power-up of the ADF4350 after the correct application of voltages to the supply pins: • Register 5 • Register 4 • Register 3 • Register 2 • ...

Page 22

ADF4350 The programmable modulus is also very useful for multi- standard applications dual-mode phone requires PDC and GSM 1800 standards, the programmable modulus is a great benefit. PDC requires 25 kHz channel step resolution, whereas GSM 1800 requires ...

Page 23

FAST LOCK—LOOP FILTER TOPOLOGY To use fast-lock mode, the damping resistor in the loop filter is reduced to ¼ of its value while in wide bandwidth mode. To achieve the wider loop filter bandwidth, the charge pump current increases by ...

Page 24

ADF4350 SPUR CONSISTENCY AND FRACTIONAL SPUR OPTIMIZATION With dither off, the fractional spur pattern due to the quantiza- tion noise of the SDM also depends on the particular phase word with which the modulator is seeded. The phase word can ...

Page 25

APPLICATIONS INFORMATION DIRECT CONVERSION MODULATOR Direct conversion architectures are increasingly being used to implement base station transmitters. Figure 34 shows how Analog Devices, Inc., parts can be used to implement such a system. The circuit block diagram shows the AD9761 ...

Page 26

ADF4350 INTERFACING The ADF4350 has a simple SPI-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 32 bits that have been clocked into the appropriate register on each ...

Page 27

OUTPUT MATCHING There are a number of ways to match the output of the ADF4350 for optimum operation; the most basic is to use a 50 Ω resistor bypass capacitor of 100 pF is connected ...

Page 28

... Model Temperature Range 1 ADF4350BCPZ −40°C to +85°C 1 ADF4350BCPZ-RL −40°C to +85°C 1 ADF4350BCPZ-RL7 −40°C to +85°C 1 EVAL-ADF4350EB1Z RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07325-0-11/08(0) 5.00 BSC SQ 0 ...

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