WM8523GEFL/RV Wolfson Microelectronics, WM8523GEFL/RV Datasheet
WM8523GEFL/RV
Specifications of WM8523GEFL/RV
Related parts for WM8523GEFL/RV
WM8523GEFL/RV Summary of contents
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... Consumer digital audio applications requiring 2Vrms output − − − − − http://www.wolfsonmicro.com/enews WM8523 106dB SNR (‘A-weighted’) -89dB THD @ -1dBFS 2 S, DSP Set Top Box Digital TV DVD Players Games Consoles A/V Receivers Pre-Production, July 2009, Rev 3.0 Copyright ©2009 Wolfson Microelectronics plc ...
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WM8523 BLOCK DIAGRAM CONTROL INTERFACE MCLK DIGITAL BCLK AUDIO LRCLK INTERFACE DACDAT w W WM8523 DIGITAL FILTERS CHARGE PUMP Pre-Production LEFT LINEVOUTL DAC RIGHT LINEVOUTR DAC PP, Rev 3.0, July 2009 2 ...
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Pre-Production DESCRIPTION ................................................................................................................... 1 FEATURES......................................................................................................................... 1 APPLICATIONS ................................................................................................................. 1 BLOCK DIAGRAM ............................................................................................................. 2 TABLE OF CONTENTS ..................................................................................................... 3 PIN CONFIGURATION ....................................................................................................... 4 ORDERING INFORMATION .............................................................................................. 4 PIN DESCRIPTION – 20-LEAD TSSOP ............................................................................ 5 PIN DESCRIPTION – 24-LEAD QFN ................................................................................. 6 ...
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... TSSOP ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8523GEDT −40°C to +85°C WM8523GEDT/R −40°C to +85°C WM8523GEFL/V −40°C to +85°C WM8523GEFL/RV −40°C to +85°C Note: TSSOP Reel quantity = 2000 QFN Reel quantity = 3500 w 24 DACDAT 1 LRCLK 2 BCLK ...
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Pre-Production PIN DESCRIPTION – 20-LEAD TSSOP PIN NO NAME TYPE 1 Analogue Out LINEVOUTL Analogue Out 2 CPVOUTN 3 Analogue Out CPCB 4 Supply LINEGND 5 Analogue Out CPCA 6 Supply LINEVDD 7 Digital Out ZFLAG Digital In 8 DACDAT ...
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WM8523 PIN DESCRIPTION – 24-LEAD QFN PIN NO NAME TYPE Digital In 1 DACDAT Digital I/O 2 LRCLK 3 Digital I/O BCLK 4 Digital In MCLK SDOUT/ 5 Digital I/O DEEMPH SDA/ 6 Digital I/O AIFMODE0 SCLK/ 7 Digital I/O ...
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Pre-Production PIN NO NAME TYPE 22 Analogue Out CPCA 23 Supply LINEVDD 24 Digital Out ZFLAG Note: Tri-level pins which require the ‘Z’ state to be selected should be left floating (open) w DESCRIPTION Charge Pump fly back capacitor pin ...
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WM8523 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...
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Pre-Production ELECTRICAL CHARACTERISTICS Test Conditions LINEVDD=AVDD=3.3V, LINEGND=AGND=0V, T stated. PARAMETER Analogue Output Levels Output Level Load Impedance Load Capacitance DAC Performance Signal to Noise Ratio Dynamic Range Total Harmonic Distortion AVDD + LINEVDD Power Supply Rejection Ratio Channel Separation System ...
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WM8523 POWER CONSUMPTION MEASUREMENTS Test Conditions LINEVDD=AVDD=3.3V, LINEGND=AGND=0V, T Off fs=48kHz, MCLK=256fs Standby Playback fs=96kHz, MCLK=256fs Standby Playback fs=192kHz, MCLK=128fs Standby Playback w =+25°C, Slave Mode, quiescent (no signal) A TEST CONDITIONS IAVDD (mA) No clocks applied 0.8 SYS_ENA[1:0]=00 SYS_ENA[1:0]=01 ...
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Pre-Production SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING Figure 1 System Clock Timing Requirements Test Conditions LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, T PARAMETER Master Clock Timing Information MCLK cycle time MCLK high time MCLK low time MCLK duty cycle (t /t MCLKH MCLKL) MCLK ...
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WM8523 AUDIO INTERFACE TIMING – SLAVE MODE Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, T PARAMETER Audio Data Input Timing Information BCLK cycle time BCLK pulse width high BCLK pulse width low LRCLK set-up ...
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Pre-Production CONTROL INTERFACE TIMING – mode is selected by driving the CIFMODE pin low. Figure 4 Control Interface Timing – I Test Conditions LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, T PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width ...
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WM8523 CONTROL INTERFACE TIMING – SPI MODE SPI mode is selected by connecting the CIFMODE pin high. Figure 5 Control Interface Timing – SPI Control Mode (Read Cycle) Test Conditions LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, T PARAMETER Program Register Input Information SCLK rising ...
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Pre-Production POWER ON RESET CIRCUIT Figure 6 Internal Power on Reset Circuit Schematic The WM8523 includes an internal Power-On-Reset circuit, as shown in Figure 6, which is used to reset the DAC digital logic into a default state after power ...
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WM8523 Test Conditions LINEVDD = AVDD = 3.3V AGND = LINEGND = 0V, T PARAMETER SYMBOL Power Supply Input Timing Information VDD level to POR defined (LINEVDD/AVDD rising) VDD level to POR rising edge V (VMID rising) VDD level to ...
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Pre-Production DEVICE DESCRIPTION INTRODUCTION The WM8523 provides high fidelity, 2V with minimal external components. The integrated DC servo eliminates the requirement for external mute circuitry by minimising DC transients at the output during power up/down. The device is well-suited to ...
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WM8523 CONTROL MODE mode, the WM8523 is a slave device on the control interface; SCLK is a clock input, while SDA is a bi-directional data pin. To allow arbitration of multiple slaves (and/or ...
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Pre-Production The sequence of signals associated with a single register write operation is illustrated in Figure 8. 2 Figure 8 Control Interface I C Register Write The sequence of signals associated with a single register read operation is illustrated in ...
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WM8523 SPI CONTROL MODE The WM8523 can also be controlled by writing to registers through a SPI control interface. A control word consists of 24 bits. The first bit is the read/write bit (R/W ¯ ¯ ), which is followed ...
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Pre-Production DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting audio data to the WM8523. The digital audio interface uses three pins: • • • In software control mode, all interface data formats and modes of operation can ...
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WM8523 AUDIO DATA FORMATS In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, ...
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Pre-Production In DSP mode, the left channel MSB is available on either the 1 BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may ...
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WM8523 Figure 22 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave) DIGITAL AUDIO INTERFACE CONTROL The control of the audio interface in software mode is achieved by register write. Dynamically changing the audio data format may cause erroneous operation and ...
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Pre-Production Interface timing is such that the input data and left/right clock are sampled on the rising edge of BCLK. By setting the appropriate BCLK and LRCLK polarity bits, the WM8523 DAC can sample data on the opposite clock edges. ...
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WM8523 DIGITAL AUDIO DATA SAMPLING RATES The external master clock is applied directly to the MCLK input pin system where there are a number of possible sources for the reference clock recommended that the clock source ...
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Pre-Production DAC FEATURES SYSTEM ENABLE The WM8523 includes a number of enable and disable mechanisms to allow the device to be powered on and off in a pop-free manner. The SYS_ENA[1:0] control bits enable the DAC and analogue paths. REGISTER ...
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WM8523 Figure 23 SYS_ENA[1:0] Power Up and Down Sequences DIGITAL VOLUME CONTROL The WM8523 DAC includes digital volume control, allowing the digital gain to be adjusted between −100dB and +12dB in 0.25dB steps. Volume update bits allow the user to ...
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Pre-Production VOLUME CHANGE MODES Volume can be adjusted by step change (either using zero cross or not soft ramp. The volume change mode is controlled by the DAC_VOL_DOWN_RAMP and DAC_VOL_UP_RAMP bits in R5: REGISTER ADDRESS R5 DAC_CTRL3 05h ...
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WM8523 Ramp Volume Changes If ramp volume changes are selected, the ramp rate is dependent upon the sampling rate. The ramp rates for common audio sample rates are shown in Table 15. SAMPLE RATE FOR DAC (kHz) Table 15 Volume ...
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Pre-Production MUTE A digital mute can be applied to left and right channels independently. REGISTER ADDRESS R5 DAC_CTRL3 05h R5 DAC_CTRL3 05h Table 18 DAC Mute Control The DAC mute function in software mode is controlled by the register settings ...
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WM8523 HARDWARE CONTROL INTERFACE The WM8523 can be controlled in hardware mode or in software modes. In hardware mode, the device is configured according to logic levels applied to hardware pins. Hardware control mode is selected by leaving CIFMODE pin ...
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Pre-Production POWER UP AND DOWN CONTROL IN HARDWARE MODE In hardware mode the MCLK, BCLK and MUTE or down, and this is summarised in Figure 25 below. Figure 25 Hardware Power Sequence Diagram Power Up To power up the device, ...
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WM8523 POWER DOMAINS Figure 26 Power Domain Diagram Power Domain Name DAC Power Supplies 3.3V ± 10% AVDD 3.3V ± 10% LINEVDD Internally Generated Power Supplies and References 1.65V ± 10% VMID -3.3V ± 10% CPVOUTN Table 23 Power Domains ...
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WM8523 REGISTER BITS BY ADDRESS REGISTER BIT LABEL ADDRESS R0 (00h) 15:0 CHIP_ID[15:0] DEVICE_ID/ SW RESET Register 00h DEVICE_ID / SW RESET REGISTER BIT LABEL ADDRESS R1 (01h) 2:0 CHIP_REV[2:0] REVISION Register 01h REVISION REGISTER BIT LABEL ADDRESS R2 (02h) ...
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Pre-Production REGISTER BIT LABEL ADDRESS R3 (03h) 8 DAC_DEEMP AIF_CTRL1 7 AIF_MSTR 6 AIF_LRCLK_ INV 5 AIF_BCLK_INV 4:3 AIF_WL[1:0] 2 Reserved 2:0 AIF_FMT[1:0] Register 03h AIF_CTRL1 w DEFAULT DESCRIPTION DAC De-emphasis Control de-emphasis 1 = De-emphasis ...
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WM8523 REGISTER BIT LABEL ADDRESS R4 (04h) 7:6 DAC_OP_ AIF_CTRL2 MUX[1:0] 5:3 AIF_ BCLKDIV[2:0] 2:0 AIF_SR[2:0] Register 04h AIF_CTRL2 REGISTER BIT LABEL ADDRESS R5 (05h) 4 DAC_ZC DAC_CTRL3 3 DACR_MUTE 2 DACL_MUTE 1 DAC_VOL_ UP_RAMP 0 DAC_VOL_ DOWN_RAMP Register 05h ...
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Pre-Production REGISTER BIT LABEL ADDRESS R6 (06h) 9 DACL_VU DAC_GAINL 8:0 DACL_VOL[8:0] Register 06h DAC_GAINL REGISTER BIT LABEL ADDRESS R7 (07h) 9 DACR_VU DAC_GAIN R 8:0 DACR_VOL[8:0] 1_1001_0000 Right DAC Digital Volume Control Register 07h DAC_GAINR REGISTER BIT LABEL ADDRESS ...
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WM8523 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS DAC Filter – 256fs to 1152fs ± 0.1dB Passband Passband Ripple Stopband Stopband attenuation f > 0.546fs Group Delay DAC Filter – 128fs and 192fs Passband ± 0.1dB Passband Ripple Stopband Stopband attenuation ...
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Pre-Production DAC FILTER RESPONSES 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) Figure 27 DAC Digital Filter Frequency Response – 256fs to 1152fs Clock Modes 0 -20 -40 -60 -80 -100 0 0.1 0.2 0.3 ...
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WM8523 DIGITAL DE-EMPHASIS CHARACTERISTICS - Frequency (kHz) Figure 31 De-Emphasis Frequency Response (32kHz) Figure 33 De-Emphasis Frequency Response (44.1kHz - Frequency (kHz) ...
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Pre-Production APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS – 20-LEAD TSSOP Figure 37 Recommended External Components Notes: 1. Wolfson recommend using a single, common ground plane. Where this is not possible, care should be taken to optimise split ground configuration for audio ...
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WM8523 RECOMMENDED PCB LAYOUT – 20-LEAD TSSOP Figure 38 Recommended PCB Layout Notes should be placed as close to WM8523 as possible, with minimal track lengths to reduce inductance and maximise performance of the charge pump. Vias should ...
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Pre-Production RECOMMENDED EXTERNAL COMPONENTS – 24-LEAD QFN Figure 39 Recommended External Components Notes: 1. Wolfson recommend using a single, common ground plane. Where this is not possible, care should be taken to optimise split ground configuration for audio performance. 2. ...
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WM8523 RECOMMENDED PCB LAYOUT – 24-LEAD QFN Figure 40 Recommended PCB Layout Notes should be placed as close to WM8523 as possible, with minimal track lengths to reduce inductance and maximise performance of the charge pump. Vias should ...
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Pre-Production RECOMMENDED ANALOGUE LOW PASS FILTER Figure 41 Recommended Analogue Low Pass Filter (one channel shown) An external single-pole RC filter is recommended if the device is driving a wideband amplifier. Other filter architectures may provide equally good results. The ...
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WM8523 PACKAGE DIMENSIONS – 20-LEAD TSSOP DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm Dimensions Symbols (mm) MIN NOM A ----- A 0. 0.80 1. 0.19 c ...
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Pre-Production PACKAGE DIMENSIONS – 24-LEAD QFN FL: 24 PIN QFN PLASTIC PACKAGE EXPOSED 6 GROUND PADDLE BOTTOM VIEW A3 SIDE VIEW C SEATING PLANE Exposed lead ...
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... WM8523 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...