5M1270ZT144I5N Altera, 5M1270ZT144I5N Datasheet

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5M1270ZT144I5N

Manufacturer Part Number
5M1270ZT144I5N
Description
ALTERA
Manufacturer
Altera
Series
MAX® Vr
Datasheets

Specifications of 5M1270ZT144I5N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of Gates
-
Number Of I /o
114
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Vendor undefined / RoHS Compliant

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MAX V Device Handbook
MAX V Device Handbook
101 Innovation Drive
San Jose, CA 95134
www.altera.com
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Related parts for 5M1270ZT144I5N

5M1270ZT144I5N Summary of contents

Page 1

... MAX V Device Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com MAX V Device Handbook Subscribe ...

Page 2

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 3

... LVDS and RSDS Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32 Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32 Output Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33 Programmable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33 Slew-Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34 Open-Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34 Programmable Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34 Bus-Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34 Programmable Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35 Programmable Input Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35 January 2011 Altera Corporation Contents MAX V Device Handbook ...

Page 4

... IEEE Std. 1149.1 Boundary-Scan Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1 JTAG Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4 Parallel Flash Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4 In-System Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5 IEEE 1532 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6 Jam Standard Test and Programming Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6 MAX V Device Handbook or V Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 CCIO CCINT Contents January 2011 Altera Corporation ...

Page 5

... Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–36 ALTUFM Parallel Interface Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–37 Instantiating Parallel Interface Using Quartus II ALTUFM_PARALLEL Megafunction . . . . . . 7–37 None (Altera Serial Interface 7–38 Instantiating None Using Quartus II ALTUFM_NONE Megafunction . . . . . . . . . . . . . . . . . . . . 7–38 Creating Memory Content File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–39 Memory Initialization for the ALTUFM_PARALLEL Megafunction . . . . . . . . . . . . . . . . . . . . . . 7–39 Memory Initialization for the ALTUFM_SPI Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7– ...

Page 6

... Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15 Boundary-Scan Description Language Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–16 Additional Information Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 MAX V Device Handbook Contents January 2011 Altera Corporation ...

Page 7

... This section provides a complete overview of all features relating to the MAX device family. This section includes the following chapters: ■ Chapter 1, MAX V Device Family Overview ■ Chapter 2, MAX V Architecture ■ Chapter 3, DC and Switching Characteristics for MAX V Devices January 2011 Altera Corporation Section I. MAX V Device Core MAX V Device Handbook ® V ...

Page 8

... I–2 MAX V Device Handbook Section I: MAX V Device Core January 2011 Altera Corporation ...

Page 9

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 10

... CCINT ) are 1.2 V, 1.5 V, 1.8 V, 2.5 V, CCIO chapter. January 2011 Altera Corporation ...

Page 11

... For more information about the In-System Sources and Probes Editor, refer to the Design Debugging Using In-System Sources and Probes Handbook. Device Pin-Outs f For more information, refer to the January 2011 Altera Corporation (Note 1) 68-Pin 100-Pin 100-Pin MBGA TQFP MBGA — ...

Page 12

... Pin Count Number of pins for a particular package Changes Updated “Feature Summary” section. Initial release. Chapter 1: MAX V Device Family Overview Ordering Information N Optional Suffix Indicates specific device options or shipment method N: Lead-free packaging ° ° ° ° 100 C) J January 2011 Altera Corporation ...

Page 13

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 14

... MAX V Device Handbook IOE IOE IOE IOE Logic Logic Element Element Logic Logic Element Element Logic Logic Element Element Logic Logic Element Element MultiTrack Interconnect chapter. Chapter 2: MAX V Architecture Functional Description IOE Logic Array BLock (LAB) Hot Socketing December 2010 Altera Corporation ...

Page 15

... Not applicable to T144 package of the 5M240Z device. (3) Only applicable to T144 package of the 5M240Z device. (4) Not applicable to F324 package of the 5M1270Z device. (5) Only applicable to F324 package of the 5M1270Z device. December 2010 Altera Corporation LAB Rows LAB Columns Long LAB Rows Short LAB Rows (Width) ...

Page 16

... LAB. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the LUT output from one LE to the MAX V Device Handbook (Note 1) UFM Block CFM Block Chapter 2: MAX V Architecture Logic Array Blocks Logic Array Blocks 2 GCLK Inputs December 2010 Altera Corporation ...

Page 17

... LAB or IOE DirectLink interconnect to adjacent LAB or IOE Logic Element Note to Figure 2–3: (1) Only from LABs adjacent to IOEs. December 2010 Altera Corporation ® II software places associated logic within an LAB or Figure 2–3 shows the MAX V LAB. Row Interconnect LE0 LE1 LE2 LE3 LE4 ...

Page 18

... DirectLink connection. DirectLink interconnect to left Local Interconnect Logic Element Chapter 2: MAX V Architecture Logic Array Blocks DirectLink interconnect from right LAB or IOE output LE0 LE1 LE2 LE3 LE4 LE5 DirectLink LE6 interconnect to right LE7 LE8 LE9 LAB December 2010 Altera Corporation ...

Page 19

... LAB Column Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local labclk1 Interconnect December 2010 Altera Corporation Figure 2–5 shows the LAB control signal labclkena1 labclkena2 syncload labclk2 asyncload or labpre 2–7 labclr2 addnsub labclr1 synclr MAX V Device Handbook ...

Page 20

... ADATA Clear Logic ENA CLRN Register Feedback Carry-Out0 Carry-Out1 LAB Carry-Out Chapter 2: MAX V Architecture Logic Elements Programmable Register LUT chain routing to next LE Row, column, and DirectLink Q routing Row, column, and DirectLink routing Local routing Register chain output December 2010 Altera Corporation ...

Page 21

... The Quartus II software, along with parameterized functions such as the library of parameterized modules (LPM) functions, automatically chooses the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. December 2010 Altera Corporation “MultiTrack Interconnect” on page MAX V Device Handbook 2–9 ...

Page 22

... LAB carry-in signal selects either the carry-in0 or Chapter 2: MAX V Architecture Logic Elements 2–7. The Quartus II Compiler aload (LAB Wide) ALD/PRE Row, column, and ADATA Q DirectLink routing D Row, column, and ENA DirectLink routing CLRN Local routing LUT chain connection Register chain output December 2010 Altera Corporation ...

Page 23

... LUT and the next portion of the carry chain. Carry-select chains can begin in any LE within an LAB. December 2010 Altera Corporation sload sclear ...

Page 24

... LE5 B6 Sum7 A7 LE6 B7 Sum8 A8 LE7 B8 Sum9 A9 LE8 B9 Sum10 A10 LE9 B10 LAB Carry-Out MAX V Device Handbook LAB Carry-In Carry-In0 Carry-In1 data1 data2 Carry-Out0 To top of adjacent LAB Chapter 2: MAX V Architecture Logic Elements LUT Sum LUT LUT LUT Carry-Out1 December 2010 Altera Corporation ...

Page 25

... FIFO synchronous R/W FIFO asynchronous R/W ■ ■ 1 port SRAM ■ 2 port SRAM ■ 3 port SRAM ■ shift registers f For more information about memory, refer to the User Guide. December 2010 Altera Corporation 2–13 Internal Memory (RAM and ROM) MAX V Device Handbook ...

Page 26

... R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive. R4 interconnects can also drive C4 interconnects for connections from one row to another. MAX V Device Handbook shows R4 interconnect connections from an LAB. R4 interconnects Chapter 2: MAX V Architecture MultiTrack Interconnect December 2010 Altera Corporation ...

Page 27

... LE to connect directly to the register input of the next LE in the LAB for fast shift registers. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. shows the LUT chain and register chain interconnects. December 2010 Altera Corporation Adjacent LAB can drive onto another C4 Column Interconnects (1) LAB’ ...

Page 28

... Routing Among LEs in the LAB LE0 LUT Chain Register Chain Routing to Routing to Adjacent Adjacent LE LE's Register Input LE1 Local LE2 Interconnect LE3 LE4 LE5 LE6 LE7 LE8 LE9 Chapter 2: MAX V Architecture MultiTrack Interconnect Figure 2–12 shows the C4 December 2010 Altera Corporation ...

Page 29

... Figure 2–12. C4 Interconnect Connections Row Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect Note to Figure 2–12: (1) Each C4 interconnect can drive either up or down four rows. December 2010 Altera Corporation (Note 1) Local Interconnect 2–17 C4 Interconnect Drives Local and R4 Interconnects Up to Four Rows C4 Interconnect ...

Page 30

... December 2010 Altera Corporation ...

Page 31

... LAB clock signals and one LAB clear signal. Other control signal types route from the global clock network into the LAB local interconnect. For more information, refer to December 2010 Altera Corporation Figure 2–13. These four pins can also be used as GPIOs if ...

Page 32

... LAB column clocks in I/O block regions provide high fan-out output enable signals. (2) LAB column clocks drive to the UFM block. MAX V Device Handbook UFM Block (2) CFM Block Chapter 2: MAX V Architecture Global Signals LAB Column clock[3..0] 4 I/O Block Region December 2010 Altera Corporation ...

Page 33

... Program, erase, and busy signals ■ Auto-increment addressing ■ Serial interface to logic array with programmable interface Figure 2–15. UFM Block and Interface Signals December 2010 Altera Corporation shows the UFM block and interface signals. The logic array is UFM Block PROGRAM Program Erase ...

Page 34

... UFM block contains an Chapter 2: MAX V Architecture User Flash Memory Block Table 2–3 lists the data Address Bits Data Width ™ Plug-In December 2010 Altera Corporation ...

Page 35

... SPI are also automatically generated in LE logic by the Quartus II software. f For more information about the UFM interface signals and the Quartus II LE-based alternate interfaces, refer to the December 2010 Altera Corporation chapter. User Flash Memory in MAX V Devices 2–23 chapter. ...

Page 36

... Figure 2–16. The interface regions for Figure CFM Block UFM Block LAB PROGRAM ERASE OSC_ENA LAB RTP_BUSY DRDin DRCLK DRSHFT ARin ARCLK LAB ARSHFT DRDout OSC BUSY Chapter 2: MAX V Architecture User Flash Memory Block 2–17. (Note 1), (2) December 2010 Altera Corporation ...

Page 37

... Figure 2–17: (1) Only applicable to the T144 package of the 5M240Z device. Core Voltage The MAX V architecture supports a 1.8-V core voltage on the V use a 1.8 Figure 2–18. Core Voltage Feature in MAX V Devices December 2010 Altera Corporation CFM Block RTP_BUSY BUSY OSC DRDout DRDin DRDCLK ...

Page 38

... Quartus II software automatically routes the register to guarantee zero hold time. You can set timing assignments in the Quartus II software to achieve desired I/O timing. MAX V Device Handbook Chapter 2: MAX V Architecture I/O Structure Figure 2–19 shows the MAX V December 2010 Altera Corporation ...

Page 39

... Data_out OE Notes to Figure 2–19: (1) Available only in I/O bank 3 of 5M1270Z and 5M2210Z devices. (2) The programmable pull-up resistor is active during power-up, in-system programming (ISP), and if the device is unprogrammed. December 2010 Altera Corporation 2–20, Figure 2–21, and Figure 2–22 DEV_OE Optional PCI Clamp (1) ...

Page 40

... Interconnect Direct Link from Adjacent LAB Interconnect to Adjacent LAB Chapter 2: MAX V Architecture I/O Structure (Note 1) I/O Block Local Interconnect data_out [6.. [6..0] 7 Row fast_out I/O Block [6.. Row I/O Block Contains up to LAB Column Seven IOEs clock [3..0] December 2010 Altera Corporation ...

Page 41

... I/O Standards and Banks Table 2–4 lists the I/O standards supported by MAX V devices. Table 2–4. MAX V I/O Standards (Part I/O Standard 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS December 2010 Altera Corporation Column I/O Block data_out OE fast_out [3..0] [3..0] [3.. ...

Page 42

... PCI compliant I/O is not supported in these All I/O Banks Support 3.3-V LVTTL/LVCMOS, 2.5-V LVTTL/LVCMOS, 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, 1.2-V LVCMOS (3), LVDS (4) , RSDS (5) Chapter 2: MAX V Architecture I/O Structure Output Supply Voltage (V ) CCIO (V) 3.3 2.5 2.5 (Note 1), (2) I/O Bank 2 December 2010 Altera Corporation ...

Page 43

... I/O pins. The pins TMS, TDI, TDO, and TCK support all the I/O standards shown in Table 2–4 on page 2–29 for all MAX V devices and their I/O standard support is controlled by the V setting for Bank 1. December 2010 Altera Corporation 2–4. PCI compliant I/O is supported in Bank 3. Bank 3 supports the I/O Bank 2 All I/O Banks Support 3 ...

Page 44

... PCI All Speed Grades All Speed Grades 144 TQFP 256 FBGA 324 FBGA — — — — — — — — — 49 eTx — — 49 eTx 75 eTx — 42 eTx 90 eTx 115 eTx — 83 eTx 115 eTx December 2010 Altera Corporation ...

Page 45

... I/O standard. The maximum, where the V OUT OL the I condition The programmable drive strength feature can be used simultaneously with the slew-rate control feature. December 2010 Altera Corporation Table 2–7 lists the possible settings for the I/O standards (Note 1) IOH/IOL Current Strength Setting (mA ...

Page 46

... The bus-hold circuitry is only active after the device has fully initialized. The bus-hold circuit captures the value on the pin present at the moment user mode is entered. MAX V Device Handbook Chapter 2: MAX V Architecture I/O Structure December 2010 Altera Corporation ...

Page 47

... VCCIO (V) 1.2 V 1 — — 1 — 1 — 1.8 — — — 2.5 December 2010 Altera Corporation level of the output pin’s bank. CCIO Table 2–8 summarizes MAX V MultiVolt I/O support. (Note 1) 2.5 V 3.3 V 5.0 V 1 — — — — — ...

Page 48

... V 3.3 V 5.0 V 1 (4) (5) (6) from rising above 4.0 V. Use an external diode if the I/O pin does not support the clamp I Changes Chapter 2: MAX V Architecture Document Revision History Output Signal 1.8 V 2.5 V 3 (6) (6) (6) (7) December 2010 Altera Corporation ...

Page 49

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 50

... MAX V device ISP and/or user flash memory (UFM) programming using JTAG or logic array is not guaranteed outside the recommended operating conditions (for example, if brown-out occurs in the system during a potential write/program sequence to the UFM, Altera recommends that you read back the UFM contents and verify it against the intended write data). ...

Page 51

... Hysteresis for Schmitt V (8) SCHMITT trigger input (9) V supply current CCINT I CCPOWERUP during power-up (10) Value of I/O pin pull-up R resistor during user PULLUP mode and ISP January 2011 Altera Corporation (Note 1) (Part Conditions Minimum = V max (2) –10 I CCIO max (2) –10 O CCIO 5M40Z, 5M80Z, 5M160Z, and 5M240Z (Commercial grade) — ...

Page 52

... Conditions Minimum — — — — — — = 1.2, 1.5, 1.8, 2.5, or 3.3 V. CCIO time. CONFIG . CCIO Operating Conditions Typical Maximum Unit — 300 µA — — settings (3.3, 2.5, 1.8, 1.5, CCIO typical value is 300 mV SCHMITT January 2011 Altera Corporation ...

Page 53

... High-level output voltage OH V Low-level output voltage OL Note to Table 3–5: (1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the MAX V Device Architecture chapter. January 2011 Altera Corporation (Note 1) MAX V Output Drive 0.0 0.5 2 ...

Page 54

... V IH Operating Conditions Maximum Unit 3.6 V 4.0 V 0.8 V — V 0.2 V Maximum Unit 2.625 V 4.0 V 0.7 V — V — V — V 0.2 V 0.4 V 0.7 V Maximum Unit 1.89 V 2.25 (2) V 0.35 × CCIO — V 0.45 V parameter I January 2011 Altera Corporation ...

Page 55

... I/O supply voltage CCIO V Differential output voltage swing OD V Output offset voltage OS Note to Table 3–12: (1) Supports emulated LVDS output using a three-resistor network (LVDS_E_3R). January 2011 Altera Corporation Conditions Minimum — 1.425 — 0.65 × V CCIO — –0.3 IOH = –2 mA (1) 0.75 × V ...

Page 56

... Operating Conditions Typical Maximum Unit 2.5 2.625 V — 600 mV 1.25 1.375 V 2.5 V 3.3 V Unit Min Max Min Max 50 — 70 — µA –50 — –70 — µA — 300 — 500 µA — –300 — –500 µA January 2011 Altera Corporation ...

Page 57

... Power Consumption You can use the Altera Analyzer to estimate the device power. f For more information about these power analysis tools, refer to the Power Estimator for Altera CPLDs User Guide in volume 3 of the Quartus II Handbook. January 2011 Altera Corporation Device Min 5M40Z — ...

Page 58

... Timing Model and Specifications MAX V devices timing can be analyzed with the Altera Quartus of industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure MAX V devices have predictable internal delays that allow you to determine the worst-case timing of any design. The software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for device-wide performance evaluation ...

Page 59

... This design is configured for read-only operation in Extended mode. Read and write ability increases the number of logic elements (LEs) used. (3) This design is configured for read-only operation. Read and write ability increases the number of LEs used. (4) This design is asynchronous. 2 (5) The I C megafunction is verified in hardware up to 100-kHz serial clock line rate. January 2011 Altera Corporation Preliminary ...

Page 60

... Table 3–18 timing microparameters for LEs, input/output elements (IOEs), UFM blocks, and MultiTrack interconnects. f For more information about each internal timing microparameters symbol, refer to AN629: Understanding Timing in Altera Table 3–18. LE Internal Timing Microparameters for MAX V Devices Symbol Parameter LE combinational look-up t ...

Page 61

... LVCMOS 2 mA — 1.2-V LVCMOS 3 mA — 3.3-V PCI 20 mA — LVDS — — RSDS — — January 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Min Max Min Max — 1,319 — 1,543 — 1,045 — 1,276 — ...

Page 62

... January 2011 Altera Corporation ...

Page 63

... Address register data in t setup to address register ADS clock Address register data in t hold from address ADH register clock t Data register clock period DCLK January 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Max Min Max Min 171 — 174 — ...

Page 64

... January 2011 Altera Corporation µ ...

Page 65

... UFM block timing parameters listed in Figure 3–3. UFM Read Waveform ARShft t t ASU ARClk ARDin t DRShft ADS DRClk DRDin DRDout OSC_ENA Program Erase Busy January 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Min Max Min Max — 65 — 65 250 — 250 — 250 — ...

Page 66

... Timing Model and Specifications t DSH t t OSCH OSCS PPMX t OSCH EPMX 5M1270Z/ 5M2210Z Unit C4 C5, I5 Max Min Max 561 — 690 ps 445 — 548 ps 731 — 899 ps January 2011 Altera Corporation ...

Page 67

... LVTTL or for different drive strengths, use the I/O standard input and output delay adders in f For more information about each external timing parameters symbol, refer to AN629: Understanding Timing in Altera Table 3–26 lists the external I/O timing parameters for the 5M40Z, 5M80Z, 5M160Z, and 5M240Z devices. ...

Page 68

... Min 10 pF — 8.1 — — 4.8 — — 1.5 — 1.9 — 0 — 2.0 5.9 2.0 — 216 — 266 January 2011 Altera Corporation C5, I5 Unit Max — ps — ns 118.3 MHz C5, I5 Unit Max 17.7 ns 8.5 ns — ns — ns 8.7 ns — ps — ...

Page 69

... Parameter t Worst case pin-to-pin delay through one LUT PD1 t Best case pin-to-pin delay through one LUT PD2 t Global clock setup time SU t Global clock hold time H January 2011 Altera Corporation (Note 1), (2) (Part Condition Min Max Min — 216 — 266 — ...

Page 70

... C4 C5, I5 Min Max Min Max — 0 — 0 — 480 — 591 — 0 — 0 — 480 — 591 — 246 — 303 — 787 — 968 — 695 — 855 — 1,334 — 1,642 January 2011 Altera Corporation Unit ...

Page 71

... LVCMOS Trigger Without Schmitt 3.3-V PCI Trigger Table 3–34. External Timing Output Delay and t I/O Standard Min 16 mA — 3.3-V LVTTL 8 mA — January 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Max Min Max — 1,055 — 1,010 — ...

Page 72

... Max 6,612 — 6,293 ps 7,313 — 6,994 ps 6,612 — 6,293 ps 7,313 — 6,994 ps 10,021 — 9,702 ps 10,881 — 10,562 ps 21,134 — 20,815 ps 22,399 — 22,080 ps 34,499 — 34,180 ps 36,281 — 35,962 ps 55,796 — 55,477 ps 339 — 418 ps January 2011 Altera Corporation ...

Page 73

... LVTTL 1.8-V LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.3-V PCI Table 3–38. Maximum Output Clock Rate for I/Os for MAX V Devices (Part 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL January 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Max Min Max Min 1,858 — ...

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... MHz 120 MHz 304 MHz 304 MHz 200 MHz 5M2210Z Unit C4, C5, I5 Max 304 Mbps 304 Mbps 304 Mbps 304 Mbps 304 Mbps 304 Mbps 304 Mbps 304 Mbps 304 Mbps 304 Mbps 55 % 0.2 UI 450 ps 450 ps January 2011 Altera Corporation ...

Page 75

... RISE t FALL Notes to Table 3–40: (1) For the input clock pin to achieve 200 Mbps, use I/O standard with V (2) This specification is based on external clean clock source. January 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z/5M1270Z/ Mode Min 10 — 9 — 8 — ...

Page 76

... V CCIO1 = 2.5 V CCIO1 = 1.8 V CCIO1 = 1.5 V CCIO1 (2) (2) (2) (2) Timing Model and Specifications t JPXZ Min Max Unit 55.5 — ns 62.5 — ns 100 — ns 143 — — — — — ns — — — — — ns — — January 2011 Altera Corporation ...

Page 77

... Document Revision History Table 3–42 lists the revision history for this chapter. Table 3–42. Document Revision History Date Version January 2011 1.1 December 2010 1.0 January 2011 Altera Corporation Parameter , t , and t are maximum values at 35 ns. JPCO JPZX JPXZ Changes Updated Table 3– ...

Page 78

... MAX V Device Handbook Chapter 3: DC and Switching Characteristics for MAX V Devices Document Revision History January 2011 Altera Corporation ...

Page 79

... Chapter 5, Using MAX V Devices in Multi-Voltage Systems ■ Chapter 6, JTAG and In-System Programmability in MAX V Devices Chapter 7, User Flash Memory in MAX V Devices ■ Chapter 8, JTAG Boundary-Scan Testing in MAX V Devices ■ January 2011 Altera Corporation Section II. System Integration in MAX V Devices ® V devices. MAX V Device Handbook ...

Page 80

... II–2 MAX V Device Handbook Section II: System Integration in MAX V Devices January 2011 Altera Corporation ...

Page 81

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 82

... V Power Supplies CCIO CCINT power supplies before or during power up. A MAX V device may CCINT and V CCIO | < 300 A. IOPIN | < for less. IOPIN supplies to the device are stable in the CC MAX V Hot-Socketing Specifications “Power-On power supplies in any CCINT December 2010 Altera Corporation ...

Page 83

... The hot-socketing circuitry prevents the I/O pins from internally powering V CCIO powered. f For more information about the 5.0-V tolerance, refer to the Multi-Voltage Systems December 2010 Altera Corporation or V power supplies) or power-down event. The hot-socketing CCIO ramps up very slowly during power up within the recommended operating range even though SRAM ...

Page 84

... ESD current discharge path during a positive Source Gate PMOS N+ Drain P-Substrate Drain Gate N+ NMOS Source GND is powered CCIO . This also applies for CCIO leakage current charges the PAD Ensures 3.3-V Tolerance and Hot-Socket The Larger of Protection VCCIO or VPAD n+ I GND December 2010 Altera Corporation ...

Page 85

... This period of time is specified as t timing section of the Entry into user mode is gated by whether all the V sufficient operating voltage device enters user mode within the t than t after V CONFIG banks are powered. December 2010 Altera Corporation Figure Source D Gate PMOS N+ Drain P-Substrate ...

Page 86

... Tri-State Operation profile shown. If this is not the case, t CCINT Changes Document Revision History and V voltage CCINT CCIO voltage sag below 1.4 V CCINT and CCINT time has CONFIG CCINT t CONFIG User Mode Operation stretches out until all CONFIG December 2010 Altera Corporation ...

Page 87

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 88

... LVTTL/LVCMOS ■ 1.5-V LVCMOS ■ 1.2-V LVCMOS ■ Emulated LVDS output (LVDS_E_3R) ■ Emulated RSDS output (RSDS_E_3R) Individual Power Bus I/O Bank 4 I/O Standards I/O Bank 3 also supports the 3.3-V PCI I/O Standard I/O Bank 3 ® II software. December 2010 Altera Corporation ...

Page 89

... V. To make MAX V device outputs compatible with 5.0-V CMOS devices, configure the output pins as open-drain pins with the I/O clamp diode enabled and use an external pull-up resistor. December 2010 Altera Corporation Figure 5–2 shows how to implement a multiple-voltage system for 1 ...

Page 90

... OL depends on the programmable drive strength of the OL lists the programmable drive strength settings that are available I/O Standard I OH 5.0-V Device Compatibility 5.0 V ± 0.5 V CCIO R EXT 5.0-V CMOS Device supplied to CCIO /I Current Strength Setting (mA December 2010 Altera Corporation ...

Page 91

... Because MAX V devices are 3.3-V, 32-bit, 66-MHz PCI compliant, the input circuitry accepts a maximum high-level input voltage (V with a 5.0-V device, you must connect a resistor (R the 5.0-V device. December 2010 Altera Corporation I/O Standard , first calculate the model of the open-drain EXT by I ...

Page 92

... V, which meets the MAX V devices reliability OH , first calculate the model of the pull- 150 135 120 V CCINT V CCIO 90 I Typical O Output Current (mA Output Voltage (V) O 5.0-V Device Compatibility MAX V Device 3 CCIO V CCIO PCI Clamp ( specifications of the devices ) by dividing the 5 5 December 2010 Altera Corporation ...

Page 93

... Notes to Table 5–3: ( the voltage at the package pin. IN (2) The I is calculated with a 3.3 December 2010 Altera Corporation 5– 5.0 V/135 mA. 1 value is 30. 1 specification is not violated. For example mA, given the I/O clamp diode follows: 2   ...

Page 94

... For signals with a duty cycle greater than 30% on MAX V input pins, Altera recommends using a V signals with a duty cycle less than 30%, the V Power-Up Sequencing MAX V devices are designed to operate in multi-voltage environments where it may be difficult to control power sequencing. Therefore, MAX V devices are designed to tolerate any possible power-up sequence ...

Page 95

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 96

... Allows you to define the scan chain between the TDI and TDO pins in the MAX V logic array. Use this instruction for custom logic and JTAG interfaces. IEEE 1532 in-system concurrent (ISC) instructions used if programming a MAX V device through the JTAG port. December 2010 Altera Corporation ...

Page 97

... Not applicable to F324 package of the 5M1270Z device. (6) Only applicable to F324 package of the 5M1270Z device. f For JTAG direct current (DC) characteristics, refer to the Characteristics for MAX V Devices December 2010 Altera Corporation Table 6–2 and Table 6–3 list the boundary-scan register length and Device ...

Page 98

... For more information about PFL, refer to the Guide. MAX V Device Handbook Chapter 6: JTAG and In-System Programmability in MAX V Devices chapter. Parallel Flash Loader Megafunction User IEEE Std. 1149.1 Boundary-Scan Support JTAG Boundary-Scan Testing for December 2010 Altera Corporation ...

Page 99

... ISP” on page These devices also offer an ISP_DONE bit that provides safe operation if in-system programming is interrupted. This ISP_DONE bit, which is the last bit programmed, prevents all I/O pins from driving until the bit is programmed. December 2010 Altera Corporation MAX V Device DQ[7..0] A[20..0] ...

Page 100

... Exit ISP—An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. MAX V Device Handbook Chapter 6: JTAG and In-System Programmability in MAX V Devices IEEE 1532 BSDL Files page of the Altera website. AN 425: Using Command-Line Jam STAPL Solution for In-System Programmability December 2010 Altera Corporation ...

Page 101

... I/O pins with weak pull-up resistors for the duration of the ISP sequence. However, some systems may require certain pins on MAX V devices to maintain a specific DC logic level during an in-field update. For these systems, you can use the optional in- system programming clamp instruction in the MAX V circuitry to control I/O December 2010 Altera Corporation 5M40Z/ 5M80Z/ 5M240Z ...

Page 102

... You can program MAX V devices by downloading the information through in-circuit testers, embedded processors, the Altera ByteBlaster™ II, EthernetBlaster, and USB-Blaster cables. BP Microsystems, System General, and other programming hardware manufacturers provide programming support for Altera devices. For device support information, refer to their websites. Document Revision History Table 6–5 lists the revision history for this document. Table 6– ...

Page 103

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 104

... MAX V Device Handbook Chapter 7: User Flash Memory in MAX V Devices Address Range 100h 1FFh 000h 0FFh Table 7–3 lists the different data Data Widths (Bits Options 7–13. January 2011 Altera Corporation UFM Array Description Interface Types Serial Serial Parallel Serial ...

Page 105

... A high value shifts the data from ARDin serially into the address register. A low value Input ARSHFT increments the current address by 1. The address register rolls over to 0 when the address space is at the maximum. January 2011 Altera Corporation UFM Block PROGRAM Program Erase ...

Page 106

... UFM block during real-time ISP. f For more information about the interaction between the UFM block and the logic array of MAX V devices, refer to the MAX V Device Handbook Chapter 7: User Flash Memory in MAX V Devices UFM Functional Description Description MAX V Device Architecture chapter. January 2011 Altera Corporation ...

Page 107

... A clock edge with the ARSHFT signal low increments the address register by 1. This implements an auto-increment of the address to allow data streaming. When a program, read, or erase sequence is executing, the address that is in the address register becomes the active UFM location. January 2011 Altera Corporation ...

Page 108

... UFM. After the program or erase algorithm is completed, the BUSY signal is forced low. MAX V Device Handbook MAX V UFM Block 16 16 Data Register D10 D11 Chapter 7: User Flash Memory in MAX V Devices UFM Functional Description DRDout D12 D13 D14 D15 DRCLK MSB January 2011 Altera Corporation ...

Page 109

... UFM memory block. ALTUFM_OSC megafunction instantiation in the Quartus II software. Figure 7–4. The Quartus II ALTUFM_OSC Megafunction January 2011 Altera Corporation “Software Support for UFM Block” on page Plug-In Manager to instantiate the UFM oscillator if you intend to use 7–7 7– ...

Page 110

... MAX V Device Handbook Chapter 7: User Flash Memory in MAX V Devices (Figure 7–7) and erase mode (Figure AN 100: In-System Programmability MAX V Device Architecture UFM Operating Modes Figure 7–5 through 7–8), the PROGRAM and ERASE Guidelines. January 2011 Altera Corporation ...

Page 111

... Figure 7–6. UFM Stream Read Waveforms ARSHFT ARCLK ARDin DRSHFT DRCLK DRDin DRDout OSC_ENA PROGRAM ERASE BUSY January 2011 Altera Corporation Figure 7–5 shows the UFM control waveforms during read mode. Figure 7–6 shows the UFM control waveforms t 9 Address Bits ACLK ASU ...

Page 112

... ARDin t ADS DRSHFT DRCLK DRDin DRDout OSC_ENA PROGRAM ERASE BUSY MAX V Device Handbook Chapter 7: User Flash Memory in MAX V Devices ADH 16 Data Bits DSH DCLK DSS t DDH t DDS t OSCS t PB January 2011 Altera Corporation UFM Operating Modes Figure 7–7 shows t OSCH PPMX ...

Page 113

... UFM array is 16 bits for each location. Figure 7–8. UFM Erase Waveforms ARSHFT DRSHFT OSC_ENA PROGRAM January 2011 Altera Corporation (Figure 7–2 on page illustrates the UFM waveforms during erase mode. 9 Address Bits t t ACLK ...

Page 114

... For information about UFM operation during ISP, refer to Programmability MAX V Device Handbook Chapter 7: User Flash Memory in MAX V Devices TM or ByteBlaster Guidelines. Programming and Reading the UFM with JTAG TM II parallel port download TM Standard Test and AN 100: In-System January 2011 Altera Corporation ...

Page 115

... Software Support for UFM Block Software Support for UFM Block The Altera Quartus II software includes sophisticated tools that fully utilize the advantages of the UFM block in MAX V devices, while maintaining simple, easy-to- use procedures that accelerate the design process. The following section describes ...

Page 116

... These inputs set the UFM slave address. The A are programmable, set internally to 1010 by default. Figure 7–9 shows the start and stop conditions. Chapter 7: User Flash Memory in MAX V Devices Software Support for UFM Block , slave address bits SDA SCL P Stop Condition January 2011 Altera Corporation ...

Page 117

... ALTUFM_I2C megafunction. You can connect these ports input pins in the design file and connect them to switches on the board. The other option is to connect them to V conserves pins. January 2011 Altera Corporation 2 Figure 7–10 shows the acknowledge condition on the ...

Page 118

... Figure 7–12 shows the byte write sequence. A Byte Address A R/W "0" (write) Chapter 7: User Flash Memory in MAX V Devices Software Support for UFM Block LSB R LSB R LSB R/W 2 Data A P From Master to Slave From Slave to Master January 2011 Altera Corporation ...

Page 119

... Data can be initialized into memory for read/write and read-only modes by including a memory initialization file (.mif) or hexadecimal file (.hex) in the ALTUFM MegaWizard Plug-In Manager. This data is automatically written into the UFM during device programming by the Quartus II software or third-party programming tool. January 2011 Altera Corporation 7–17 “Erase MAX V Device Handbook ...

Page 120

... The master should Slave Address 111 '0' (write) S – Start Condition P – Stop Condition A – Acknowledge Software Support for UFM Block slave address bits transmitted 0 shows the full erase sequence P From Master to Slave From Slave to Master January 2011 Altera Corporation ...

Page 121

... If the ALTUFM_I2C megafunction is write-protected (WP=1), the slave does not acknowledge the byte address (that indicates the UFM sector to be erased) sent in by the master. The master should then send a stop condition to terminate the transfer and the sector erase operation will not be executed. January 2011 Altera Corporation Triggered ...

Page 122

... P – Stop Condition A – Acknowledge MAX V Device Handbook shows the current address read sequence. Slave Address S A R/W ‘1’ (read) Chapter 7: User Flash Memory in MAX V Devices Software Support for UFM Block Data P From Master to Slave From Slave to Master January 2011 Altera Corporation ...

Page 123

... Figure 7–17. Sequential Read Sequence Slave S A R/W Address ‘0’ (write) S – Start Condition Sr – Repeated Start P – Stop Condition A – Acknowledge January 2011 Altera Corporation Byte Slave A Sr Address Address ‘1’ (read) Byte Slave A Sr ...

Page 124

... Min Max — 501 — 1,002 Software Support for UFM Block t SU:STO t BUF Max Unit 100 kHz 15 ns — µs — µs — µs — µs — µs — ns — ns — ns Unit µs Unit ms ms January 2011 Altera Corporation ...

Page 125

... With the ALTUFM megafunction, the UFM and MAX V logic can be configured as a slave device for the SPI bus. The OSC_ENA is always asserted to enable the internal oscillator when the SPI megafunction is instantiated for both read only and read/write interfaces. January 2011 Altera Corporation 2 C Interface Using the Quartus II ALTUFM_I2C 2 C Interface Instantiation in the Quartus 7– ...

Page 126

... Op-Code Decoder Read, Write, and Erase State Machine Address and Data Hub Eight-Bit Status Shift Register Software Support for UFM Block Table 7–9 describes the SPI Function SI SO SCK nCS SPI Interface Control Logic January 2011 Altera Corporation ...

Page 127

... Bit 0 nRDY Note to Table 7–11: (1) For more information about status register bits BP1 and BP0, refer to The following sections describe the instructions for SPI. January 2011 Altera Corporation Opcode Enable Write to UFM 00000110 Disable Write to UFM 00000100 Read Status Register 00000101 ...

Page 128

... Figure 7–21. READ Operation Sequence for Extended Mode nCS SCK 8-bit Instruction MSB High Impedance SO MAX V Device Handbook 16-bit Address MSB 16-bit Data Out 1 MSB Chapter 7: User Flash Memory in MAX V Devices Software Support for UFM Block Figure 7–21: 16-bit Data Out 2 MSB January 2011 Altera Corporation ...

Page 129

... WRITE operation is ignored and not accepted 8-bit address is received. A check is carried out on the status register (see Table 7–11) to determine if the WRITE operation has been enabled, and the address is outside of the protected region; otherwise, Step 4 is skipped. January 2011 Altera Corporation 8-bit Address MSB ...

Page 130

... MAX V Device Handbook 16-bit Address 16-bit Data In MSB MSB 8-bit 8-bit Instruction Address 02 8-bit Data In H MSB High Impedance Chapter 7: User Flash Memory in MAX V Devices Software Support for UFM Block Figure 7–25: January 2011 Altera Corporation ...

Page 131

... Opcode 00100000 is transmitted into the interface. 3. nCS is pulled back to high. Figure 7–25. SECTOR-ERASE Operation Sequence for Extended Mode Figure 7–26 shows the SECTOR-ERASE operation sequence for Base mode. Figure 7–26. SECTOR_ERASE Operation Sequence for Base Mode January 2011 Altera Corporation nCS ...

Page 132

... Figure 7–27 shows the UFM-ERASE operation sequence. Figure 7–27. UFM-ERASE Operation Sequence MAX V Device Handbook Chapter 7: User Flash Memory in MAX V Devices Figure 7–27: nCS SCK 8-bit Instruction MSB High Impedance SO Software Support for UFM Block January 2011 Altera Corporation ...

Page 133

... After the transmission of the eighth bit of WREN, the interface is in wait state (waiting for nCS to be pulled back to high). Any transmission after this is ignored. 4. nCS is pulled back to high. Figure 7–28. WREN Operation Sequence January 2011 Altera Corporation Table 7–11 power-up. Before any write is allowed to take Figure 7– ...

Page 134

... Any transmission after this is ignored. 4. nCS is pulled back to high. Figure 7–29. WRDI Operation Sequence MAX V Device Handbook Chapter 7: User Flash Memory in MAX V Devices Figure 7–29: nCS SCK 8-bit Instruction MSB High Impedance SO Software Support for UFM Block January 2011 Altera Corporation ...

Page 135

... SI ignores incoming signals; SO outputs the content of the status register, Bit 7 first and Bit 0 last nCS is kept low, repeat step 3. 5. nCS is pulled back to high to terminate the transmission. Figure 7–30. RDSR Operation Sequence nCS SCK SI SO January 2011 Altera Corporation 8-bit ...

Page 136

... Status Register In H MSB MSB High Impedance SO Status Register Bits BP1 BP0 Status Register Bits BP1 BP0 Software Support for UFM Block Table 7–13 lists UFM Array Address Protected None 000 to 1FF UFM Array Address Protected None 000 to 0FF January 2011 Altera Corporation ...

Page 137

... Manager as discussed in 1 The UFM block’s internal oscillator is always running when the ALTUFM_SPI megafunction is instantiated for read/write interface. The UFM block’s internal oscillator is disabled when the ALTUFM_SPI megafunction is instantiated for read only interface. January 2011 Altera Corporation t HNCSHIGH t t NCS2SCK ...

Page 138

... ADDR[] port. Driven low to notify that it is not available to respond to any further request. Driven high to indicate that the data at the DO port is the valid data from the last read address for read request. Software Support for UFM Block January 2011 Altera Corporation ...

Page 139

... Instantiating Parallel Interface Using Quartus II ALTUFM_PARALLEL Megafunction Figure 7–35 shows the ALTUFM_PARALLEL megafunction symbol for a parallel interface instantiation in the Quartus II software. Figure 7–35. ALTUFM_PARALLEL Megafunction Symbol for Parallel Interface Instantiation January 2011 Altera Corporation t COMMAND t HNBUSY t HBUS Description 7– ...

Page 140

... ALTUFM MegaWizard Plug-In Manager as discussed in “Creating Memory Content MAX V Device Handbook Chapter 7: User Flash Memory in MAX V Devices “Creating Memory Content File” on Table 7–4 on page 7–3. You can produce your own File”. January 2011 Altera Corporation Software Support for UFM Block ...

Page 141

... You can put valid data for SPI Base mode addresses 0 to 255 (sector 0), and initialize sector 1 to all ones. January 2011 Altera Corporation 7–39 MAX V Device Handbook ...

Page 142

... An 8-bit wide and 1,024 deep (10-bit address) mapping for 8 Kbits memory size ■ Altera recommends that you pad the .mif or .hex file for both address and data width to fill the physical memory map for the UFM block and ensure the .mif or .hex file represents a full 16-bit word size and a 9-bit address space ...

Page 143

... UFM block address location of 000h to 07Fh. The ALTUFM_I2C megafunction byte address location of 80h to FFh is mapped to the UFM block address location of 180h to 1FFh. Altera recommends that you pad the unused address location of the UFM block with all 1s. Figure 7–38. Memory Map for 2-Kbit Memory Initialization ...

Page 144

... The lower quarter of logical memory maps to the lower byte of sector 0. Address 000h in logical memory maps to address 000h in physical memory and all addresses follow the order in logical memory. Lower 8-bit (byte) 16-bit data in UFM January 2011 Altera Corporation ...

Page 145

... Document Revision History Table 7–17 lists the revision history for this chapter. Table 7–17. Document Revision History Date Version January 2011 1.1 December 2010 1.0 January 2011 Altera Corporation 8-bit valid data to be placed Pad the lower byte with eight '1's ...

Page 146

... MAX V Device Handbook Chapter 7: User Flash Memory in MAX V Devices Document Revision History January 2011 Altera Corporation ...

Page 147

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 148

... Therefore, you must set up the TMS before the rising edge of TCK. TMS is evaluated on the rising edge of TCK. The clock input to the BST circuitry. Some operations occur at Test clock input the rising edge, while others occur at the falling edge. IEEE Std. 1149.1 BST Architecture Function December 2010 Altera Corporation ...

Page 149

... TDO pin as an output. The boundary-scan register consists of 3-bit peripheral elements that are associated with the I/O pins of the MAX V devices. You can use the boundary-scan register to test the external pin connections or to capture internal data. December 2010 Altera Corporation Instruction Register Instruction Decode Data Registers ...

Page 150

... TDI pin and ends at the TDO pin of the device. MAX V Device Handbook Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices Internal Logic TAP Controller TDI TMS TCK IEEE Std. 1149.1 Boundary-Scan Register Each peripheral element is either an I/O pin, dedicated input pin, or dedicated configuration pin. TDO December 2010 Altera Corporation ...

Page 151

... TDI, TDO, TMS, and TCK pins and all VCC and GND pin types do not have BSCs. JTAG Pins and Power Pins MAX V devices do not have BSCs for dedicated JTAG pins (TDI, TDO, TMS, and TCK) and power pins (VCCINT, VCCIO, GNDINT, and GNDIO). December 2010 Altera Corporation SDO 0 D ...

Page 152

... TMS = 1 TMS = 1 EXIT1_DR TMS = 0 TMS = 0 PAUSE_DR TMS = 0 TMS = 1 TMS = 1 TMS = 0 TMS = 0 EXIT2_DR TMS = 1 TMS = 1 TMS = 1 TMS = 1 UPDATE_DR TMS = 0 IEEE Std. 1149.1 BST Operation Control JTAG chapter. SELECT_IR_SCAN CAPTURE_IR SHIFT_IR TMS = 0 TMS = 1 EXIT1_IR PAUSE_IR TMS = 0 EXIT2_IR UPDATE_IR TMS = 0 December 2010 Altera Corporation ...

Page 153

... From the RESET state, TMS is clocked with the pattern 01100 to advance the TAP controller to SHIFT_IR state. Figure 8–7. Selecting the Instruction Mode TCK TMS TDI TDO TAP_STATE RUN_TEST/IDLE SELECT_DR_SCAN TEST_LOGIC/RESET December 2010 Altera Corporation (Note JCP JPSU t t JCH JCL t t ...

Page 154

... For MAX V devices, there are weak pull-up resistors for TDI and TMS, and pull-down resistors for TCK. However JTAG chain, there might be some devices that do not have internal pull-up or pull-down resistors. In this case, Altera recommends pulling the TMS pin high (through an external 10-k resistor), and pulling TCK low (through an external 1-k ...

Page 155

... TMS is held low. The data shifted out of the TDO pin consists of the data that was present in the capture registers after the capture phase. New test data shifted into the TDI pin appears at the TDO pin after being clocked through the entire boundary-scan register. December 2010 Altera Corporation SDO PIN_IN D ...

Page 156

... Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices SELECT_DR_SCAN Data stored in boundary- scan CAPTURE_DR register is shifted out of TDO. IEEE Std. 1149.1 BST Operation Control SHIFT_DR After boundry-scan EXIT1_DR register data has been UPDATE_DR shifted out, data entered into TDI will shift out of TDO. December 2010 Altera Corporation ...

Page 157

... EXTEST mode. Figure 8–10. IEEE Std. 1149.1 BST EXTEST Mode INJ 0 1 OEJ 0 1 OUTJ 0 1 SHIFT SDI INJ 0 1 OEJ 0 1 OUTJ 0 1 SHIFT SDI December 2010 Altera Corporation SDO PIN_IN D Q Input PIN_OE PIN_OUT ...

Page 158

... TCK pulse. chapter. IEEE Std. 1149.1 BST Operation Control SHIFT_DR After boundry-scan EXIT1_DR register data has been UPDATE_DR shifted out, data entered into TDI will shift out of TDO. Bit n EXIT1_DR UPDATE_DR JTAG and In-System December 2010 Altera Corporation ...

Page 159

... I/O weak pull-up resistor or I/O bus hold if you have any of them selected. I/O Voltage Support in the JTAG Chain There can be several different Altera or non-Altera devices in a JTAG chain. However, you must pay attention to whether or not the chain contains devices with different V levels ...

Page 160

... Shift TDO to Level Must be 1.8-V Accepted by Tester Tolerant if Necessary Boundary-Scan Test for Programmed Devices on IH device. JTAG pins CCIO MAX V Device level drives to a device with CCIO Must be 3.3-V Tolerant 2.5-V V CCIO 1.8-V 1.8 CCIO CCIO Must be 2.5-V Tolerant December 2010 Altera Corporation ...

Page 161

... The BSDL—a subset of VHDL—provides a syntax that allows you to describe the features of an IEEE Std. 1149.1 BST-capable device that can be tested. Test software development systems then use the BSDL files for test generation, analysis, failure diagnostics, and in-system programming. December 2010 Altera Corporation JTAG Pins (1) TCK ...

Page 162

... Table 8–4. Document Revision History Date Version December 2010 1.0 Initial release. MAX V Device Handbook Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices IEEE 1149.1 BSDL Files page on the Altera website. Changes Document Revision History December 2010 Altera Corporation ...

Page 163

... Technical training Product literature Non-technical support (General) (Software Licensing) Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Bold Type with Initial Capital ...

Page 164

... A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center website, where you can sign up to receive update notifications for Altera documents. Additional Information Typographic Conventions page of the Altera January 2011 Altera Corporation ...

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