A3930KJPTR-T Allegro Microsystems Inc, A3930KJPTR-T Datasheet
A3930KJPTR-T
Specifications of A3930KJPTR-T
A3930KJPTR-T
Available stocks
Related parts for A3930KJPTR-T
A3930KJPTR-T Summary of contents
Page 1
Automotive 3-Phase BLDC Controller and MOSFET Driver Features and Benefits ▪ High current 3-phase gate drive for N-channel MOSFETs ▪ Synchronous rectification ▪ Cross-conduction protection ▪ Charge pump and top-off charge pump for 100% PWM ▪ Integrated commutation decoder logic ...
Page 2
... The dead time can be set by a single external resistor. The A3930 and A3931 only differ in their response to the all-zero Selection Guide Part Number Option A3930KJPTR-T Hall short detection A3931KJPTR-T Pre-positioning Absolute Maximum Ratings Parameter Load Supply Voltage ...
Page 3
A3930 and A3931 VBAT+ V5BD QV5 +5V Ref V5 CV5 MODE COAST BRAKE RESET DIR RDEAD PWM TACHO DIRO ESF Diagnostics and Protection –UVLO FF1 –TSD –Short to Supply –Short to Ground –Shorted Winding FF2 –Low Load ...
Page 4
A3930 and A3931 ELECTRICAL CHARACTERISTICS Characteristics Supply and Reference VBB Functional Operating Range 6 VBB Quiescent Current V5 Quiescent Current VREG Output Voltage Bootstrap Diode Forward Voltage Bootstrap Diode Resistance Bootstrap Diode Current Limit Top-off Charge Pump Current Limit High-Side ...
Page 5
A3930 and A3931 ELECTRICAL CHARACTERISTICS (continued) Characteristics Turn-Off Propagation Delay Dead Time (turn-off to turn-on delay) Logic Inputs and Outputs FFx Fault Output (Open Drain) FFx Fault Output Leakage Current 2 TACHO and DIRO Output High Voltage TACHO and DIRO ...
Page 6
A3930 and A3931 ELECTRICAL CHARACTERISTICS (continued) Characteristics Supply Rejection Small Signal 3 dB Bandwidth Frequency Settling Time AC Common Mode Gain Common Mode Recovery Time Output Slew Rate Input Overload Recovery Time Current Limit Reference Comparator Input Offset Voltage Reference ...
Page 7
A3930 and A3931 may require derating at maximum conditions, see Applications Information section THERMAL CHARACTERISTICS Characteristic Package Thermal Resistance Die-to-Exposed Pad Thermal Resis- tance *Additional thermal information available on Allegro Web site. Power Dissipation versus Ambient Temperature Automotive 3-Phase BLDC ...
Page 8
A3930 and A3931 Basic Operation The A3930 and A3931 devices provide commutation and current control for 3-phase brushless DC (BLDC) motors with integrated Hall-effect (HE) sensors. The motor current is provided by an external 3-phase N-channel MOSFET bridge which is ...
Page 9
A3930 and A3931 In order to provide a known start-up position for the motor, an optional prepositioning function is available in the A3931. When the Hall inputs are all driven low ( 0), the power ...
Page 10
A3930 and A3931 greater than 20 kΩ. The upper limit for the resistor must be low enough to ensure that the input voltage reaches the input high threshold INR COAST An active-low input which turns all FETs off ...
Page 11
A3930 and A3931 In some circumstances, it may be desirable to completely disable the internal PWM control. This can be done by pulling the RC pin directly to AGND. This will disable the internal PWM oscil- lator and ensure that ...
Page 12
A3930 and A3931 In addition to a monitor on VREG, the A3930/A3931 also monitors both the bootstrap charge voltage, to ensure sufficient high-side drive, and the 5 V reference voltage at V5, to ensure correct logical operation. If either of ...
Page 13
A3930 and A3931 Table 1. Fault Action Table FF1 FF2 Fault 0 0 Undervoltage 0 0 Overtemperature 0 0 Logic Fault 1 0 Short to ground 1 0 Short to supply 1 0 Shorted motor winding 0 1 Low load ...
Page 14
A3930 and A3931 Power All supply connections to the A3930/A3931 should have capaci- tors mounted between the supply pins and the ground pin. These capacitors will provide the transient currents which occur during switching and decouple any voltage transients on ...
Page 15
A3930 and A3931 high-side PWM cycle is requested. The minimum time required to charge the capacitor is approximated by: ≈ C × ΔV /250 mA t CHARGE(min) BOOT At power-on, and when the drivers have been disabled for a long ...
Page 16
A3930 and A3931 Note that this blank time is only used to mask the internal cur- rent comparator. If the current sense amplifier output, CSOUT, is being used in an external PWM control circuit, then it will be necessary to ...
Page 17
A3930 and A3931 Circuit Layout Because this is a switch-mode application, where rapid current changes are present, care must be taken during layout of the application PCB. The following points are provided as guidance for layout (refer to figure 3). ...
Page 18
A3930 and A3931 to limit fast transient voltage spikes caused by trace induc- tance. 6. Ensure that the TEST pin is connected to AGND. This pin is used for production test only. The above are only recommendations. Each application is ...
Page 19
A3930 and A3931 Gate Drive Outputs GHx VREG GLx 20 V LSS Supplies CP1 CP2 VDRAIN Logic Inputs COAST ESF 3 k ...
Page 20
A3930 and A3931 Terminal List Table Number Name 1 N.C. No connection 2 RESET Control for sleep mode 3 V5BD 5V regulator base drive regulator reference 5 FF2 Fault flag 2 6 FF1 Fault flag 1 7 ...
Page 21
A3930 and A3931 Package JP, 48-pin LQFP with Exposed Thermal Pad 9.00 ±0.20 7.00 ±0.20 B 9.00 ±0.20 7.00 ±0. 5.00±0.04 48X 0.08 C 0.22 ±0.05 0.50 Copyright ©2006-2010, Allegro MicroSystems, Inc. The products described here ...