AD5338BRM Analog Devices Inc, AD5338BRM Datasheet - Page 6

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AD5338BRM

Manufacturer Part Number
AD5338BRM
Description
Dual 10Bit DAC, 2Wire ITF 2.5v -5.5V I.C
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD5338BRM

Rohs Status
RoHS non-compliant
Settling Time
7µs
Number Of Bits
10
Data Interface
Serial
Number Of Converters
2
Voltage Supply Source
Single Supply
Power Dissipation (max)
1.9mW
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
AD5338BRM
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD5338BRMZ
Manufacturer:
ADI/亚德诺
Quantity:
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AD5337/AD5338/AD5339
TIMING CHARACTERISTICS
V
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
C
1
2
SCL
1
2
3
4
5
6
7
8
9
10
11
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
C
B
DD
1
B
is the total capacitance of one bus line in pF; t
= 2.5 V to 5.5 V. All specifications T
SDA
SCL
t
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
0
300
20 + 0.1 C
400
9
A Version and B Version
CONDITION
START
Limit at T
t
4
B
2
t
3
MIN
, T
MAX
MIN
R
and t
t
10
to T
t
6
F
measured between 0.3 V
MAX
Figure 2. 2-Wire Serial Interface Timing Diagram
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
, unless otherwise noted.
t
2
Rev. C | Page 6 of 28
Conditions/Comments
SCL clock frequency
SCL cycle time
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Capacitive load for each bus line
t
HIGH
LOW
HD, STA
SU, DAT
HD, DAT
HD, DAT
SU, STA
SU, STO
BUF
R
R
F
F
F
F
11
, fall time of SDA when transmitting
, fall time of SDA when receiving (CMOS compatible)
, fall time of SCL and SDA when receiving
, fall time of SCL and SDA when transmitting
, rise time of SCL and SDA when receiving
, rise time of SCL and SDA when receiving (CMOS compatible)
DD
, bus free time between a stop and a start condition
, SCL low time
t
, SCL high time
5
and 0.7 V
, setup time for repeated start
, start/repeated start condition hold time
, data setup time
, stop condition setup time
, data hold time
, data hold time
IH
min of the SCL signal) to bridge the undefined region of SCL’s falling edge.
DD
.
CONDITION
REPEATED
START
t
7
t
4
t
1
CONDITION
STOP
t
8

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