AD5339ARMZ Analog Devices Inc, AD5339ARMZ Datasheet - Page 4

• Manufacturer Part Number: AD5339ARMZ
• Description: Dual 12Bit DAC, 2Wire ITF 2.5v -5.5V I.C
• Manufacturer: Analog Devices Inc

Specifications of AD5339ARMZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5337/AD5338/AD5339
Parameter
LOGIC INPUTS (A0)
LOGIC INPUTS (SCL, SDA)
LOGIC OUTPUT (SDA)
POWER REQUIREMENTS
1
2
3
4
5
6
7
Temperature range for A Version and B Version: −40°C to +105°C; typical at 25°C.
See the Terminology section for explanations of the specific parameters.
DC specifications tested with the outputs unloaded.
Linearity is tested using a reduced code range: AD5337 (Code 8 to Code 248), AD5338, AD5338-1 (Code 28 to Code 995), AD5339 (Code 115 to Code 3981).
Guaranteed by design and characterization; not production tested.
For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, V
I
DD
Input Current
Input Low Voltage (V
Input High Voltage (V
Pin Capacitance
Input High Voltage (V
Input Low Voltage (V
Input Leakage Current (I
Input Hysteresis (V
Input Capacitance (C
Glitch Rejection
Output Low Voltage (V
Three-State Leakage Current
Three-State Output Capacitance
V
I
I
DD
DD
specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
DD
V
V
V
V
(Normal Mode)
(Power-Down Mode)
DD
DD
DD
DD
= 4.5 V to 5.5 V
= 2.5 V to 3.6 V
= 4.5 V to 5.5 V
= 2.5 V to 3.6 V
2
5
7
HYST
5
IN
IL
IL
IH
IH
)
)
)
)
5
)
)
OL
IN
)
)
Min
2.4
2.1
2.0
0.7 ×
V
−0.3
0.05 ×
V
2.5
DD
DD
A Grade
Typ
3
8
8
300
250
0.2
0.08
1
Max
±1
0.8
0.6
0.5
V
0.3
+0.3
V
±1
50
0.4
0.6
±1
5.5
375
350
1.0
1.00
DD
DD
Rev. C | Page 4 of 28
+
Min
2.4
2.1
2.0
0.7 ×
V
–0.3
0.05 ×
V
2.5
DD
DD
B Grade
Typ
3
8
8
300
250
0.2
0.08
1
Max
±1
0.8
0.6
0.5
V
0.3
+0.3
V
±1
50
0.4
0.6
±1
5.5
375
350
1.0
1.00
DD
DD
+
REF
= V
DD
Unit
μA
V
V
V
V
V
V
pF
V
V
μA
V
pF
ns
V
V
μA
pF
V
μA
μA
μA
μA
and offset plus gain error must be positive.
Conditions/Comments
V
V
V
V
V
V
SMBus compatible at
V
SMBus compatible at
V
Input filtering suppresses
noise spikes of less than
50 ns
I
I
V
V
I
readback on SDA
I
readback on SDA
SINK
SINK
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
IH
IH
= 1.5 μA (max) during 0
= 4 μA (max) during 0
= V
= V
= 5 V ± 10%
= 3 V ± 10%
= 2.5 V
= 5 V ± 10%
= 3 V ± 10%
= 2.5 V
< 3.6 V
< 3.6 V
= 3 mA
= 6 mA
DD
DD
and V
and V
IL
IL
= GND
= GND