AD5339BRMZ

Manufacturer Part NumberAD5339BRMZ
DescriptionDual 12Bit DAC, 2Wire ITF 2.5v -5.5V I.C
ManufacturerAnalog Devices Inc
AD5339BRMZ datasheet
 


Specifications of AD5339BRMZ

Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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FEATURES
AD5337
2 buffered 8-bit DACs in 8-lead MSOP
AD5338, AD5338-1
2 buffered 10-bit DACs in 8-lead MSOP
AD5339
2 buffered 12-bit DACs in 8-lead MSOP
Low power operation: 250 μA @ 3 V, 300 μA @ 5 V
2
2-wire (I
C-compatible) serial interface
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
3 power-down modes
Double-buffered input logic
Output range: 0 V to V
REF
Power-on reset to 0 V
Simultaneous update of outputs (LDAC function)
Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
SCL
INTERFACE
SDA
LOGIC
A0
POWER-ON
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
2.5 V to 5.5 V, 250 μA, 2-Wire Interface,
Dual Voltage Output, 8-/10-/12-Bit DACs
GENERAL DESCRIPTION
The AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit
buffered voltage output DACs, respectively. Each part is housed
in an 8-lead MSOP package and operates from a single 2.5 V to
5.5 V supply, consuming 250 μA at 3 V. On-chip output amplifiers
allow rail-to-rail output swing with a slew rate of 0.7 V/μs. A 2-
wire serial interface operates at clock rates up to 400 kHz. This
interface is SMBus compatible at V
can be placed on the same bus.
The references for the two DACs are derived from one reference
pin. The outputs of all DACs can be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on reset circuit to ensure that the DAC outputs power up
to 0 V and remain there until a valid write to the device takes
place. A software clear function resets all input and DAC
registers to 0 V. A power-down feature reduces the current
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip-
ment. The power consumption is typically 1.5 mW at 5 V and
0.75 mW at 3 V, reducing to 1 μW in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
V
REFIN
DD
LDAC
INPUT
DAC
STRING
REGISTER
REGISTER
DAC A
INPUT
DAC
STRING
REGISTER
REGISTER
DAC B
AD5337/AD5338/AD5339
RESET
GND
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD5337/AD5338/AD5339
< 3.6 V. Multiple devices
DD
V
A
BUFFER
OUT
BUFFER
V
B
OUT
POWER-DOWN
LOGIC
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