12-BIT 65 MSPS MONOLITHIC A/D CONVERTER

 

AD6640ASTZ

Manufacturer Part NumberAD6640ASTZ
Description12-BIT 65 MSPS MONOLITHIC A/D CONVERTER
ManufacturerAnalog Devices Inc
AD6640ASTZ datasheet
 

Specifications of AD6640ASTZ

FunctionA/D ConverterRf TypeCellular/PCS, GPS
Secondary Attributes12 Bit, 65MSPSPackage / Case44-LQFP
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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FEATURES
65 MSPS Minimum Sample Rate
80 dB Spurious-Free Dynamic Range
IF Sampling to 70 MHz
710 mW Power Dissipation
Single 5 V Supply
On-Chip T/H and Reference
Twos Complement Output Format
3.3 V or 5 V CMOS Compatible Output Levels
APPLICATIONS
Cellular/PCS Base Stations
Multichannel, Multimode Receivers
GPS Anti-Jamming Receivers
Communications Receivers
Phased Array Receivers
GENERAL DESCRIPTION
The AD6640 is a high speed, high performance, low power,
monolithic 12-bit analog-to-digital converter. All necessary
functions, including track-and-hold (T/H) and reference, are
included on-chip to provide a complete conversion solution.
The AD6640 runs on a single 5 V supply and provides CMOS
compatible digital outputs at 65 MSPS.
Specifically designed to address the needs of multichannel,
multimode receivers, the AD6640 maintains 80 dB spurious-
free dynamic range (SFDR) over a bandwidth of 25 MHz.
Noise performance is also exceptional: typical signal-to-noise
ratio is 68 dB.
The AD6640 is built on Analog Devices’ high speed complemen-
tary bipolar process (XFCB) and uses an innovative multipass
architecture. Units are packaged in a 44-lead plastic quad flatpack
(LQFP) specified from –40°C to +85°C.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
12-Bit, 65 MSPS
IF Sampling A/D Converter
FUNCTIONAL BLOCK DIAGRAM
AV
DV
CC
CC
AIN
TH1
TH2
BUF
AIN
2.4V
ADC
DAC
V
REF
REFERENCE
6
ENCODE
INTERNAL
DIGITAL ERROR CORRECTION LOGIC
TIMING
ENCODE
MSB
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
GND
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate is 65 MSPS.
2. Fully differential analog input stage specified for frequencies
up to 70 MHz; enables IF sampling.
3. Low power dissipation: 710 mW off a single 5 V supply.
4. Digital outputs may be run on 3.3 V supply for easy interface
to digital ASICs.
5. Complete solution: reference and track-and-hold.
6. Packaged in small, surface-mount 44-lead plastic LQFP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD6640
A
TH3
ADC
7
AD6640
LSB
www.analog.com

AD6640ASTZ Summary of contents

  • Page 1

    FEATURES 65 MSPS Minimum Sample Rate 80 dB Spurious-Free Dynamic Range IF Sampling to 70 MHz 710 mW Power Dissipation Single 5 V Supply On-Chip T/H and Reference Twos Complement Output Format 3 CMOS Compatible ...

  • Page 2

    AD6640–SPECIFICATIONS DC SPECIFICATIONS ( Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error 1 Differential Nonlinearity (DNL) 1 Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error POWER SUPPLY REJECTION RATIO (PSRR) 2 REFERENCE ...

  • Page 3

    SWITCHING SPECIFICATIONS Parameter (Conditions) Maximum Conversion Rate 2 Minimum Conversion Rate Aperture Delay ( Aperture Uncertainty (Jitter) 3 ENCODE Pulsewidth High ENCODE Pulsewidth Low Output Delay ( 3.3 V/5 NOTES 1 All ...

  • Page 4

    AD6640 1 ABSOLUTE MAXIMUM RATINGS Parameter ELECTRICAL AV Voltage CC DV Voltage CC Analog Input Voltage Analog Input Current Digital Input Voltage (ENCODE) Digital Output Current 2 ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) ...

  • Page 5

    Pin No. Name 1, 2, 36, 37, 40 ENCODE ENCODE 13, 14, 17, 18, 21, GND 22, 24, 34, 35, 38 AIN AIN REF 10 C1 11, 12, ...

  • Page 6

    AD6640 DEFINITION OF SPECIFICATIONS Analog Bandwidth (Small Signal) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between a differential crossing ...

  • Page 7

    ANALOG ENCODE INPUTS DIGITAL OUTPUTS AIN BUF 450 V CL BUF 450 AIN BUF V CL Figure 2. Analog Input Stage 17k ENCODE TIMING R2 CIRCUITS 8k ...

  • Page 8

    AD6640 –Typical Performance Characteristics 0 ENCODE = 65MSPS AIN = 2.2MHz 100 120 dc 6.5 13.0 19.5 FREQUENCY – MHz TPC 1. Single Tone at 2.2 MHz 0 ...

  • Page 9

    ENCODE = 65MSPS AIN = 15.0MHz, 16.0MHz NO DITHER 100 120 dc 6.5 13.0 19.5 FREQUENCY – MHz TPC 7. Two Tones at 15.0 MHz and 16.0 MHz 100 90 dBFS 80 70 ENCODE = ...

  • Page 10

    AD6640 0 ENCODE = 65MSPS AIN = 19.5MHz @ –36dBFS –20 NO DITHER –40 –60 –80 –100 –120 dc 6.5 13.0 19.5 FREQUENCY – MHz TPC 13. 16K FFT without Dither 100 90 ENCODE = 65MSPS 80 AIN = 19.5MHz ...

  • Page 11

    THEORY OF OPERATION The AD6640 analog-to-digital converter (ADC) employs a two- stage subrange architecture. This design approach ensures 12-bit accuracy, without the need for laser trim, at low power. As shown in the functional block diagram, the AD6640 has complementary ...

  • Page 12

    AD6640 T1–1T SINE SOURCE R Figure 11. Sine Source–Differential ENCODE If a low jitter ECL clock is available, another option is to ac-couple a differential ECL signal to the ENCODE input pins as shown in Figure 12. The capacitors shown ...

  • Page 13

    The addition of small value resistors between the AD9631 and the AD6640 will prevent oscillation due to the capacitive input of the ADC. AD9631 62 SIGNAL SOURCE 467 78 350 1000 OP279 OP279 (1/2) (1/2) 750 0.1 F ...

  • Page 14

    AD6640 AD6640 output data is latched using 74LCX574 (U3, U4) latches following 348 Ω series resistors. The resistors limit the current that would otherwise flow due to the digital output slew rate. The resistor value was chosen to represent a ...

  • Page 15

    U5 348 74LVQ00 (+5VA 0 ENCODE INPUT 100 T4– ENCODE ENCODE ...

  • Page 16

    AD6640 Figure 19. AD6640ST/PCB Top Side Silkscreen Figure 20. AD6640ST/PCB Bottom Side Silkscreen NOTE: Evaluation boards are often updated; consult factory for latest version. Figure 21. AD6640ST/PCB Top Side Copper Figure 22. AD6640ST/PCB Bottom Side Copper (Positive) –16– REV. A ...

  • Page 17

    Figure 23. AD6640ST/PCB Ground Layer (Negative) REV. A Figure 24. AD6640ST/PCB “Split” Power Layer (Negative) –17– AD6640 ...

  • Page 18

    AD6640 NARROWBAND NARROWBAND LNA FILTER FILTER e.g. 900MHz FIXED VARIABLE SHARED ONE RECEIVER PER CHANNEL Figure 25. Narrowband Digital Receiver Architecture If demodulation takes place in the analog domain, then tradi- tional discriminators, envelop detectors, ...

  • Page 19

    PRESELECT 5MHz–15MHz LNA PASS BAND FILTER LO DRIVE 1900MHz M/N PLL SYNTHESIZER REF IN 65MHz REFERENCE CLOCK band-pass filter will remove harmonics generated within the amplifier, but intermods should be better than the performance of the A/D converter. In the ...

  • Page 20

    AD6640 The signal-to-noise ratio (SNR) for an ADC can be predicted. When normalized to ADC codes, the following equation accurately predicts the SNR based on jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise ...

  • Page 21

    BPF IF AMP FROM RF/IF COMBINER LPF NOISE SOURCE (SEE FIGURE 30) 0.1 F 0.01 F Figure 31. Using the AD6640 with Dither Receiver Example To determine how the ADC performance relates to overall receiver sensitivity, the simple receiver in ...

  • Page 22

    AD6640 In narrow-band applications, harmonics of the ADC can be placed out-of-band. One example is the digitization of a 201 MHz IF signal using a 17.333 MHz clock. As shown in Figure 33, the spurious performance has diminished due to ...

  • Page 23

    EIGHT WIDEBAND FRONT ENDS ANTENNA 1 AD6640 COMMON LO ANTENNA 2 AD6640 ANTENNA 3 AD6640 ANTENNA 4 AD6640 ANTENNA 5 AD6640 ANTENNA 6 AD6640 ANTENNA 7 AD6640 ANTENNA 8 AD6640 Figure 34. Receive Chain for a Phased-Array Cellular Base Station ...

  • Page 24

    AD6640 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90 CCW Revision History Location 2/03—Data Sheet changed from REV REV. A. Updated Format . . . . . . . . . . . . . ...