AD6645ASVZ-105 Analog Devices Inc, AD6645ASVZ-105 Datasheet

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AD6645ASVZ-105

Manufacturer Part Number
AD6645ASVZ-105
Description
14 Bit 105 MSPS ADC PB Free
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD6645ASVZ-105

Design Resources
Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
Number Of Bits
14
Sampling Rate (per Second)
105M
Data Interface
Parallel
Number Of Converters
4
Power Dissipation (max)
1.75W
Voltage Supply Source
Analog and Digital
Operating Temperature
-10°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
52-TQFP, 52-VQFP
Number Of Elements
1
Resolution
14Bit
Architecture
Pipelined
Sample Rate
105MSPS
Input Polarity
Unipolar
Input Type
Voltage
Rated Input Volt
±1.1V
Differential Input
Yes
Power Supply Requirement
Single
Single Supply Voltage (typ)
5V
Single Supply Voltage (min)
4.75V
Single Supply Voltage (max)
5.25V
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Differential Linearity Error
-1LSB/1.5LSB
Integral Nonlinearity Error
±1.5LSB(Typ)
Operating Temp Range
-10C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
52
Package Type
TQFP EP
Input Signal Type
Differential
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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FEATURES
SNR = 75 dB, f
SNR = 72 dB, f
SFDR = 89 dBc, f
100 dBFS multitone SFDR
IF sampling to 200 MHz
Sampling jitter: 0.1 ps
1.5 W power dissipation
Differential analog inputs
Pin compatible to AD6644
Twos complement digital output format
3.3 V CMOS compatible
Data-ready for output latching
APPLICATIONS
Multichannel, multimode receivers
Base station infrastructures
AMPS, IS-136, CDMA, GSM, W-CDMA
Single channel digital receivers
Antenna array processing
Communications instrumentation
Radars, infrared imaging
Instrumentation
GENERAL DESCRIPTION
The AD6645 is a high speed, high performance, monolithic 14-bit
analog-to-digital converter (ADC). All necessary functions,
including track-and-hold (T/H) and reference, are included on the
chip to provide a complete conversion solution. The AD6645
provides CMOS-compatible digital outputs. It is the fourth
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
ENCODE
ENCODE
VREF
AIN
AIN
IN
IN
A1
15 MHz, up to 105 MSPS
200 MHz, up to 105 MSPS
IN
2.4V
INTERNAL
AV
70 MHz, up to 105 MSPS
TIMING
GND
CC
TH1
DV
CC
DMID
ADC1
OVR
TH2
DRY
5
DAC1
MSB
FUNCTIONAL BLOCK DIAGRAM
D13
D12
A2
D11
DIGITAL ERROR CORRECTION LOGIC
Figure 1.
D10
AD6645
TH3
D9
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
generation in a wideband ADC family, preceded by the AD9042
(12-bit, 41 MSPS), the AD6640 (12-bit, 65 MSPS, IF sampling),
and the AD6644 (14-bit, 40 MSPS/65 MSPS).
Designed for multichannel, multimode receivers, the AD6645 is
part of the Analog Devices, Inc., SoftCell® transceiver chipset.
The AD6645 maintains 100 dB multitone, spurious-free dynamic
range (SFDR) through the second Nyquist band. This breakthrough
performance eases the burden placed on multimode digital
receivers (software radios) that are typically limited by the ADC.
Noise performance is exceptional; typical signal-to-noise ratio
(SNR) is 74.5 dB through the first Nyquist band.
The AD6645 is built on the Analog Devices extra fast
complementary bipolar (XFCB) process and uses an innovative,
multipass circuit architecture. Units are available in thermally
enhanced 52-lead PowerQuad 4 (LQFP_PQ4) and 52-lead
exposed pad (TQFP_EP) packages specified from −40°C to
+85°C at 80 MSPS and −10°C to +85°C at 105 MSPS.
PRODUCT HIGHLIGHTS
1.
2.
3.
D8
IF Sampling. The AD6645 maintains outstanding ac
performance up to input frequencies of 200 MHz, suitable
for multicarrier 3G wideband cellular IF sampling receivers.
Pin Compatibility. The ADC has the same footprint and
pin layout as the AD6644 14-bit, 40 MSPS/65 MSPS ADC.
SFDR Performance and Oversampling. Multitone SFDR
performance of 100 dBFS can reduce the requirements of
high end RF components and allows the use of receive
signal processors, such as the AD6620, AD6624/AD6624A,
or AD6636.
ADC2
TH4
14-Bit, 80 MSPS/105 MSPS
D7
5
D6
DAC2
©2002–2008 Analog Devices, Inc. All rights reserved.
D5
D4
TH5
D3
A/D Converter
D2
ADC3
D1
AD6645
www.analog.com
LSB
D0
6

Related parts for AD6645ASVZ-105

AD6645ASVZ-105 Summary of contents

Page 1

FEATURES SNR = 75 dB MHz 105 MSPS IN SNR = 72 dB, f 200 MHz 105 MSPS IN SFDR = 89 dBc MHz 105 MSPS IN 100 dBFS multitone ...

Page 2

AD6645 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 Digital Specifications ................................................................... 4 AC Specifications ...

Page 3

SPECIFICATIONS DC SPECIFICATIONS 3 and MIN MAX Table 1. Parameter Temp RESOLUTION ACCURACY No Missing Codes Full Offset Error Full Gain Error Full Differential Nonlinearity (DNL) Full Integral Nonlinearity ...

Page 4

AD6645 DIGITAL SPECIFICATIONS 3 and MIN MAX Table 2. Parameter ENCODE INPUTS (ENCODE, ENCODE) 1 Differential Input Voltage Differential Input Resistance Differential Input Capacitance LOGIC OUTPUTS (D13 to D0, ...

Page 5

Parameter WORST HARMONIC (FOURTH OR HIGHER) Analog Input @ −1 dBFS TWO-TONE SFDR 2, 3 TWO-TONE IMD REJECTION F1 −7 dBFS ANALOG INPUT BANDWIDTH 1 Analog input signal power swept from −10 dBFS to −100 dBFS ...

Page 6

AD6645 Parameter DATA-READY (DRY 4 )/DATA(D13:0),, OVR Data-Ready to DATA Delay (Hold Time) 50% Duty Cycle Data-Ready to DATA Delay (Setup Time) 50% Duty Cycle APERTURE DELAY APERTURE UNCERTAINTY (JITTER) 1 Several timing parameters are a function of t ENC ...

Page 7

... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The heat sink of the AD6645ASVZ, 52-lead TQFP_EP (SV-52-1) package must be soldered to the PCB GND plane to meet thermal specifications. Table 6. Thermal Characteristics Package Type ...

Page 8

AD6645 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ENCODE ENCODE NOTES 1. DNC = DO NOT CONNECT. 2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND. Table 7. Pin Function Descriptions Pin Number Mnemonic 1, 33 10, ...

Page 9

TYPICAL PERFORMANCE CHARACTERISTICS 0 ENCODE = 80MSPS –10 AIN = 2.2MHz @ –1dBFS SNR = 75.0dB –20 SFDR = 93.0dBc –30 –40 –50 –60 –70 –80 3 – –100 6 4 –110 –120 –130 ...

Page 10

AD6645 75.5 75 –40°C 74 +85°C 74 +25°C 73.5 73.0 72.5 ENCODE = 80MSPS @ AIN = –1dBFS TEMP = –40°C, +25°C, +85°C 72 FREQUENCY (MHz) Figure 10. Signal-to-Noise ...

Page 11

ENCODE = 80MSPS –10 AIN = 30.5MHz, 31.5MHz (–7dBFS) –20 NO DITHER –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) Figure 16. Two-Tone SFDR @ 30.5 MHz ...

Page 12

AD6645 0 ENCODE = 80.0MSPS –10 AIN = 30.5MHz @ –29.5dBFS NO DITHER –20 –30 –40 –50 –60 –70 –80 2 –90 6 –100 3 –110 5 –120 –130 FREQUENCY (MHz) Figure 22. 1 ...

Page 13

ENCODE = 76.8MSPS –10 AIN = 2W-CDMA @ 59.6MHz –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) Figure 28. Two W-CDMA Carriers @ 59.6 MHz, Encode = ...

Page 14

AD6645 EQUIVALENT CIRCUITS AIN BUF 500Ω BUF 500Ω AIN BUF V CL Figure 32. Analog Input Stage LOADS 10kΩ ENCODE 10kΩ LOADS Figure 33. Encode Inputs ...

Page 15

TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of ...

Page 16

AD6645 Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (that is, ...

Page 17

THEORY OF OPERATION The AD6645 ADC employs a three-stage subrange architecture. This design approach achieves the required accuracy and speed while maintaining low power and small die size. As shown in the functional block diagram (see Figure 1), the AD6645 ...

Page 18

AD6645 This limits the amount of dynamic current from the A/D flowing back into the secondary of the transformer. The 50 Ω impedance matching can also be incorporated on the secondary side of the transformer, as shown in the evaluation ...

Page 19

LAYOUT INFORMATION The schematic of the evaluation board (see Figure 43) represents a typical implementation of the AD6645. A multi- layer board is recommended to achieve best results highly recommended that high quality, ceramic chip capacitors be used ...

Page 20

AD6645 Table 9. AD6645/PCB Bill of Materials Quantity Quantity 80 MSPS 105 MSPS Reference PCB 4 4 C1, C2, C31, C38 C10, C16, 1 C30 , C32 9 9 C4, C15, C22 ...

Page 21

Quantity Quantity 80 MSPS 105 MSPS Reference (U8 AC-coupled AIN is standard: R3, R4, R5, R8, and U3 are not installed. If dc-coupled AIN is required, ...

Page 22

AD6645 ...

Page 23

Figure 44. Top Signal Level Figure 45. 5.0 V Plane Layer 3 and 3.3 V Plane Layer 4 Figure 46. Ground Plane Layer 2 and Ground Plane Layer 5 Figure 47. Bottom Signal Layer Rev Page 23 of ...

Page 24

... AD6645ASVZ-80 −40°C to +85°C AD6645ASQ-105 −10°C to +85°C 1 AD6645ASQZ-105 −10°C to +85°C 1 AD6645ASVZ-105 −10°C to +85°C 1 AD6645-80/PCBZ 1 AD6645-105/PCBZ RoHS Compliant Part. ©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...

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