AD6645ASVZ-105 Analog Devices Inc, AD6645ASVZ-105 Datasheet - Page 15

• Manufacturer Part Number: AD6645ASVZ-105
• Description: 14 Bit 105 MSPS ADC PB Free
• Manufacturer: Analog Devices Inc

Specifications of AD6645ASVZ-105

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
• Number Of Bits: 14
• Sampling Rate (per Second): 105M
• Data Interface: Parallel
• Number Of Converters: 4
• Power Dissipation (max): 1.75W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-TQFP, 52-VQFP
• Number Of Elements: 1
• Resolution: 14Bit
• Architecture: Pipelined
• Sample Rate: 105MSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: ±1.1V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Differential Linearity Error: -1LSB/1.5LSB
• Integral Nonlinearity Error: ±1.5LSB(Typ)
• Operating Temp Range: -10C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: TQFP EP
• Input Signal Type: Differential
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
encode command and the instant at which the analog input is
sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. The peak differential
voltage is computed by observing the voltage on a single pin and
subtracting the voltage from the other pin, which is 180° out of
phase. The peak-to-peak differential is computed by rotating the
inputs’ phase 180°and taking the peak measurement again. The
difference is then computed between both peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Encode Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the
encode pulse should be left in a high state to achieve rated
performance; pulse width low is the minimum time that
the encode pulse should be left in a low state. See timing
implications of changing t
these specifications define an acceptable encode duty cycle.
Full-Scale Input Power
The full-scale input power is expressed in dBm and can be
calculated by using the following equation:
Power
Full
−
Scale
=
10
ENCH
log
in Table 4. At a given clock rate,
⎡
⎢
⎢
⎢
⎢
⎢
⎢
⎣
V
2
Full
Z
. 0
−
Input
001
Scale
rms
⎤
⎥
⎥
⎥
⎥
⎥
⎥
⎦
Rev. D | Page 15 of 24
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Noise (for Any Range Within the ADC)
where:
Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value for the particular input level.
Signal is the signal level within the ADC reported in dB below
full scale. This value includes both thermal noise and quantiza-
tion noise.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio (PSSR)
The ratio of a change in input offset voltage to a change in
power supply voltage.
Power Supply Rise Time
The time from when the dc supply is initiated until the supply
output reaches the minimum specified operating voltage for the
ADC. The dc level is measured at the supply pin(s) of the ADC.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc.
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full scale)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc.
V
NOISE
=
Z
×
. 0
001
×
10
⎛
⎜
⎝
FS
dBm
−
SNR
dBc
10
−
Signal
AD6645
dBFS
⎞
⎟
⎠