AD6645ASVZ-105 Analog Devices Inc, AD6645ASVZ-105 Datasheet - Page 19

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AD6645ASVZ-105

Manufacturer Part Number
AD6645ASVZ-105
Description
14 Bit 105 MSPS ADC PB Free
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD6645ASVZ-105

Design Resources
Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
Number Of Bits
14
Sampling Rate (per Second)
105M
Data Interface
Parallel
Number Of Converters
4
Power Dissipation (max)
1.75W
Voltage Supply Source
Analog and Digital
Operating Temperature
-10°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
52-TQFP, 52-VQFP
Number Of Elements
1
Resolution
14Bit
Architecture
Pipelined
Sample Rate
105MSPS
Input Polarity
Unipolar
Input Type
Voltage
Rated Input Volt
±1.1V
Differential Input
Yes
Power Supply Requirement
Single
Single Supply Voltage (typ)
5V
Single Supply Voltage (min)
4.75V
Single Supply Voltage (max)
5.25V
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Differential Linearity Error
-1LSB/1.5LSB
Integral Nonlinearity Error
±1.5LSB(Typ)
Operating Temp Range
-10C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
52
Package Type
TQFP EP
Input Signal Type
Differential
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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LAYOUT INFORMATION
The schematic of the evaluation board (see Figure 43)
represents a typical implementation of the AD6645. A multi-
layer board is recommended to achieve best results. It is highly
recommended that high quality, ceramic chip capacitors be
used to decouple each supply pin to ground directly at the
device. The pinout of the AD6645 facilitates ease of use in the
implementation of high frequency, high resolution design practices.
All of the digital outputs are segregated to two sides of the chip,
with the inputs on the opposite side for isolation purposes.
Care should be taken when routing the digital output traces. To
prevent coupling through the digital outputs into the analog
portion of the AD6645, minimal capacitive loading should be
placed on these outputs. It is recommended that a fanout of
only one gate should be used for all AD6645 digital outputs.
The layout of the encode circuit is equally critical. Any noise
received on this circuitry results in corruption in the digitization
process and lower overall performance. The encode clock must be
isolated from the digital outputs and the analog inputs.
Table 8. Twos Complement Output Coding
AIN Level
VREF + 0.55 V
VREF
VREF − 0.55 V
AIN Level
VREF − 0.55 V
VREF
VREF + 0.55 V
Output State
Positive FS
Midscale
Negative FS
Output Code
01 1111 1111 1111
00 … 0/11 … 1
10 0000 0000 0000
Rev. D | Page 19 of 24
JITTER CONSIDERATIONS
The SNR for an ADC can be predicted. When normalized to
ADC codes, the following equation accurately predicts the SNR
based on three terms: jitter, average DNL error, and thermal
noise. Each of these terms contributes to the noise within the
converter.
where:
f
t
and internal encode circuitry).
ε is the average DNL of the ADC (typically 0.41 LSB).
n is the number of bits in the ADC.
V
analog input of the ADC (typically 0.9 LSB rms).
For a 14-bit ADC, such as the AD6645, aperture jitter can
greatly affect the SNR performance as the analog frequency is
increased. Figure 42 shows a family of curves that demonstrate the
expected SNR performance of the AD6645 as jitter increases.
The chart is derived from the preceding equation.
For a complete discussion of aperture jitter, see the AN-756
application note, Sampled Systems and the Effects of Clock Phase
Noise and Jitter. The AN-756 application note can be found on
www.analog.com.
SNR
20
ANALOG
j rms
NOISE rms
log
is the rms jitter of the encode (rms sum of encode source
=
80
75
70
65
60
55
. 1
is the analog input frequency.
(
2
76
is the voltage rms thermal noise that refers to the
0
π
×
f
AIN = 110MHz
ANALOG
AIN = 150MHz
0.1
×
AIN = 190MHz
t
j
Figure 42. SNR vs. Jitter
rms
0.2
)
2
+
JITTER (ps)
⎛ +
1
2
0.3
n
ε
2
+
0.4
2
×
AIN = 30MHz
AIN = 70MHz
2
×
2
0.5
V
n
NOISE
AD6645
rms
0.6
2
1
2 /

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