AD7190BRUZ-REEL Analog Devices Inc, AD7190BRUZ-REEL Datasheet
AD7190BRUZ-REEL
Specifications of AD7190BRUZ-REEL
Available stocks
Related parts for AD7190BRUZ-REEL
AD7190BRUZ-REEL Summary of contents
Page 1
FEATURES RMS noise: 8 4.7 Hz (gain = 128) 16 noise free bits @ 2.4 kHz (gain = 128 22.5 noise free bits (gain = 1) Offset drift: 5 nV/°C Gain drift: 1 ppm/°C Specified drift ...
Page 2
AD7190 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 7 Circuit and Timing Diagrams ..................................................... 7 Absolute Maximum Ratings ............................................................ ...
Page 3
SPECIFICATIONS 5.25 V, AGND = DGND = 0 V, REFINx(+) = unless otherwise noted. A MIN MAX Table 1. ...
Page 4
AD7190 Parameter AD7190B External Clock @ 50 Hz 120 120 @ 60 Hz 120 3 Sinc Filter Internal Clock @ 50 Hz ...
Page 5
Parameter AD7190B 2 Normal Mode Rejection Same as for analog inputs Common-Mode Rejection 95 Reference Detect Levels 0.3 0.6 TEMPERATURE SENSOR Accuracy ±2 Sensitivity 2815 BRIDGE POWER-DOWN SWITCH Allowable Current 30 BURNOUT CURRENTS AIN Current 500 ...
Page 6
AD7190 Parameter AD7190B 8 POWER REQUIREMENTS Power Supply Voltage AV − AGND 4.75/5. − DGND 2.7/5.25 DD Power Supply Currents AI Current 1 DD 1.3 4.5 4.75 6.2 6.75 DI Current 0.4 DD 0.6 1.5 I (Power-Down Mode) ...
Page 7
TIMING CHARACTERISTICS 5.25 V, AGND = DGND = 0 V, Input Logic Input Logic otherwise noted. Table 2. Parameter ...
Page 8
AD7190 DOUT/RDY (O) SCLK (I) SCLK ( MSB INPUT OUTPUT Figure 3. Read Cycle Timing Diagram CS ( DIN (I) ...
Page 9
ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter Rating AV to AGND −0 +6 AGND −0 +6 AGND to DGND −0 +0.3 V ...
Page 10
AD7190 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. 2 MCLK2 ...
Page 11
Pin No. Mnemonic Description 13 AIN3 Analog Input. It can be configured as the positive input of a fully differential input pair when used with AIN4 pseudo differential input when used with AINCOM. 14 AIN4 Analog Input. ...
Page 12
AD7190 TYPICAL PERFORMANCE CHARACTERISTICS 8,388,760 8,388,758 8,388,756 8,388,754 8,388,752 8,388,750 8,388,748 8,388,746 0 200 400 600 SAMPLE Figure 6. Noise ( Output Data Rate = 4.7 Hz, Gain = 128, Chop REF 4 Disabled, Sinc Filter) 250 ...
Page 13
SAMPLES Figure 10. Noise ( Output Data Rate = 4800 Hz, Gain = 1, Chop REF 4 Disabled, Sinc ...
Page 14
AD7190 –60 –40 – TEMPERATURE (°C) Figure 14. Offset Error (Gain = 1, Chop Disabled) 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –60 –40 – ...
Page 15
RMS NOISE AND RESOLUTION The AD7190 has a choice of two filter types: sinc In addition, the AD7190 can be operated with chop enabled or chop disabled. The following tables show the rms noise of the AD7190 for some of ...
Page 16
AD7190 3 SINC CHOP DISABLED Table 8. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1023 4.7 639.4 640 7.5 400 480 10 300 ...
Page 17
SINC CHOP ENABLED Table 10. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1023 1.175 1702 640 1.875 1067 480 2.5 800 96 12.5 160 80 15 133 ...
Page 18
AD7190 3 SINC CHOP ENABLED Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1023 1.56 1282 640 2.5 800 480 3.33 600 96 16.6 120 80 20 ...
Page 19
ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers, which are described in the following sections. In the descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted. ...
Page 20
AD7190 STATUS REGISTER (RS2, RS1, RS0 = Power-On/Reset = 0x80) The status register is an 8-bit, read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to ...
Page 21
Table 17. Mode Register Bit Designations Bit Location Bit Name Description MR23 to MR21 MD2 to MD0 Mode select bits. These bits select the operating mode of the AD7190 (see Table 18). MR20 DAT_STA This bit enables the transmission of ...
Page 22
AD7190 Table 18. Operating Modes MD2 MD1 MD0 Mode Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/ RDY pin and the RDY ...
Page 23
CON23 CON22 CON21 Chop(0) 0(0) 0(0) CON15 CON14 CON13 CH7(0) CH6(0) CH5(0) CON7 CON6 CON5 Burn(0) REFDET(0) 0(0) Table 19. Configuration Register Bit Designations Bit Location Bit Name Description CON23 Chop Chop enable bit. When the chop bit is cleared, ...
Page 24
AD7190 Table 20. Channel Selection Channel Enable Bits in the Configuration Register CH7 CH6 CH5 CH4 CH3 DATA REGISTER (RS2, RS1, RS0 = Power-On/Reset = 0x000000) The conversion result from the ADC ...
Page 25
GP7 GP6 GP5 0(0) BPDSW(0) GP32EN(0) Table 21. Register Bit Designations Bit Location Bit Name Description GP7 0 This bit must be programmed with a Logic 0 for correct operation BPDSW Bridge power-down switch control bit. This bit ...
Page 26
AD7190 ADC CIRCUIT INFORMATION 5V IN+ OUT+ OUT– IN– OVERVIEW The AD7190 is an ultralow noise ADC that incorporates a ∑-Δ modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range signals such as ...
Page 27
FREQUENCY (Hz) 3 Figure 20. Sinc Filter Response (50 Hz Output Data Rate) 4 The sinc filter provides 50 Hz (±1 Hz) rejection in excess ...
Page 28
AD7190 50 Hz/60 Hz Rejection Normal mode rejection is one of the main functions of the digital filter. With chop disabled rejection is obtained when the output data rate is set to 50 Hz, whereas 60 Hz rejection ...
Page 29
Hz (sinc filter rejection is no longer achieved. The ADC needs to operate with an output data rate of 12 obtain 50 Hz rejection when zero latency is enabled. To obtain simultaneous 50 ...
Page 30
AD7190 Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7190, with CS being used to decode the part. the timing for a read operation from the output shift register of the AD7190, and Figure 4 shows ...
Page 31
Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7190 converts continuously, the RDY bit in the status register going low each time a conversion is complete low, the DOUT/ RDY line also goes low ...
Page 32
AD7190 Continuous Read Rather than write to the communications register each time a conversion is complete to access the data, the AD7190 can be configured so that the conversions are placed on the DOUT/ RDY line automatically. By writing 01011100 ...
Page 33
CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL The AD7190 has two differential/four pseudo differential analog input channels which can be buffered or unbuffered. In buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into ...
Page 34
AD7190 clock source is used, the clock source must be connected to the MCLK2 pin and the MCLK1 pin must be left floating. The internal clock can also be made available at the MCLK2 pin. This is useful when several ...
Page 35
SYSTEM SYNCHRONIZATION The SYNC input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the part. This allows the user to start gathering samples of the analog input from a ...
Page 36
AD7190 ENABLE PARITY The AD7190 also has a parity check function on-chip that detects 1-bit errors in the serial communications between the ADC and the microprocessor. When the ENPAR bit in the mode register is set to 1, parity is ...
Page 37
The AD7190 gives the user access to the on-chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and also to write its own calibration coefficients from prestored values in the EEPROM. A read of the ...
Page 38
AD7190 APPLICATIONS INFORMATION The AD7190 provides a low-cost, high resolution analog-to- digital function. Because the analog-to-digital function is provided by a ∑-Δ architecture, it makes the part more immune to noisy environments, making it ideal for use in sensor measurement ...
Page 39
... OUTLINE DIMENSIONS 0.15 0.05 ORDERING GUIDE Models Temperature Range 1 AD7190BRUZ –40°C to +105°C 1 AD7190BRUZ-REEL –40°C to +105°C 1 EVAL-AD7190EBZ RoHS Compliant Part. 7.90 7.80 7. 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.30 0.20 SEATING 0.19 PLANE ...
Page 40
AD7190 NOTES ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07640-0-5/09(B) Rev Page ...