AD7193BCPZ Analog Devices Inc, AD7193BCPZ Datasheet
AD7193BCPZ
Specifications of AD7193BCPZ
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AD7193BCPZ Summary of contents
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FEATURES Fast settling filter option 4 differential/8 pseudo differential input channels RMS noise 4.7 Hz (gain = 128) 15.5 noise-free bits @ 2.4 kHz (gain = 128 noise-free bits (gain = 1) Offset drift: ...
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AD7193 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 ESD ...
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SPECIFICATIONS 5. 2 5.25 V, AGND = DGND = 0 V; REFINx(+) = 2 MCLK = 4.92 MHz unless ...
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AD7193 Parameter Min 2 Normal-Mode Rejection 4 Sinc Filter Internal Clock @ 50 Hz 100 External Clock @ 50 Hz 120 120 @ ...
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Parameter Min REFERENCE INPUT REFIN Voltage 1 Absolute REFIN Voltage AGND − 0.05 2 Limits Average Reference Input Current Average Reference Input Current Drift 2 Normal Mode Rejection Common-Mode Rejection Reference Detect Levels 0.3 TEMPERATURE SENSOR Accuracy Sensitivity BRIDGE POWER-DOWN ...
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AD7193 Parameter Min 2 SYSTEM CALIBRATION Full-Scale Calibration Limit Zero-Scale Calibration −1.05 × FS Limit Input Span 0.8 × POWER REQUIREMENTS Power Supply Voltage AV − AGND − DGND 2.7 DD Power Supply Currents AI ...
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TIMING CHARACTERISTICS 5. 2 5.25 V, AGND = DGND = 0 V, Input Logic Input Logic Table 2. Parameter Limit at ...
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AD7193 DOUT/RDY (O) SCLK (I) SCLK ( MSB INPUT OUTPUT Figure 3. Read Cycle Timing Diagram CS ( DIN (I) ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter AV to AGND AGND DD AGND to DGND Analog Input Voltage to AGND Reference Input Voltage to AGND Digital Input Voltage to DGND Digital ...
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AD7193 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 5. 28-lead TSSOP Pin Function Descriptions Pin No. Mnemonic Description 1 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. ...
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Pin No. Mnemonic Description 14 AIN4 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN3 pseudo differential input when used with AINCOM. 15 AIN5 Analog ...
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AD7193 Table 6. 32-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description 1 P3 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AV AGND Digital Output Pin. This pin can function as ...
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Pin No. Mnemonic Description 17 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can lie anywhere between but the part functions with a reference from ...
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AD7193 TYPICAL PERFORMANCE CHARACTERISTICS 8,387,486 8,387,484 8,387,482 8,387,480 8,387,478 8,387,476 8,387,474 8,387,472 8,387,470 8,387,468 0 200 400 600 SAMPLE Figure 7. Noise ( Output Data Rate = 4.7 Hz, REF DD Gain = 128, Chop ...
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V (V) IN Figure 13. INL (Gain = –5 –10 –15 –20 –0.03 –0.02 –0.01 0 0.01 V (V) ...
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AD7193 100 OUTPUT DATA RATE (Hz) 4 Figure 19. Noise Free Resolution (Sinc Filter, Chop Disabled 100 OUTPUT DATA RATE (Hz) ...
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RMS NOISE AND RESOLUTION The following tables show the rms noise, peak-to-peak noise, effective resolution, and noise free (peak-to-peak) resolution of the AD7193 for various output data rates and gain settings with 4 3 chop disabled for the sinc and ...
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AD7193 3 SINC CHOP DISABLED Table 10. RMS Noise (nV) vs. Gain and Output Data Rate Output Data Filter Word (Decimal) Rate (Hz) 1023 4.7 640 7.5 480 150 16 300 5 960 2 ...
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FAST SETTLING Table 13. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data (Decimal) Average Rate ( 42. 50. 126. 252.63 Table ...
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AD7193 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described on the following pages wherein the term set implies a Logic 1 state and the term cleared implies a Logic 0 state, ...
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COMMUNICATIONS REGISTER RS2, RS1, RS0 = 000 The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communi- cations register determine whether ...
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AD7193 STATUS REGISTER RS2, RS1, RS0 = 000; Power-On/Reset = 0x80 The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation ...
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MODE REGISTER RS2, RS1, RS0 = 001; Power-On/Reset = 0x080060 The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the ...
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AD7193 Bit Location Bit Name Description MR12 CLK_DIV Clock divide-by-2. When CLK_DIV is set, the master clock is divided by 2. For normal conversions, set this bit to 0. When performing internal full-scale calibrations, this bit must be set when ...
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MD2 MD1 MD0 Mode Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in ...
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AD7193 CONFIGURATION REGISTER RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117 The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for ...
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Bit Location Bit Name Description CON4 BUF Enables the buffer on the analog inputs. If BUF is set, the analog inputs are buffered, allowing the user to place source impedances on the front end without contributing gain errors to the ...
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AD7193 DATA REGISTER RS2, RS1, RS0 = 011; Power-On/Reset = 0x000000 The conversion result from the ADC is stored in this data register. This is a read-only, 24-bit register. Upon completion of a read operation from this register, the RDY ...
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OFFSET REGISTER RS2, RS1, RS0 = 110; Power-On/Reset = 0x800000) The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The AD7193 has five offset registers. In differential mode, ...
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AD7193 ADC CIRCUIT INFORMATION 5V IN+ OUT+ OUT– IN– OVERVIEW The AD7193 is an ultralow noise ADC that incorporates a Σ-Δ modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range signals such as ...
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ANALOG INPUT CHANNEL The AD7193 has four differential/eight pseudo differential analog input channels that can be buffered or unbuffered. In buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into a high ...
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AD7193 REFERENCE DETECT The AD7193 includes on-chip circuitry to detect whether the part has a valid reference for conversions or calibrations. This feature is enabled when the REFDET bit in the configuration register is set the voltage ...
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In continuous conversion mode, the ADC selects each of the enabled channels in sequence and performs a conversion on the channel. The DOUT/ RDY pin indicates when a valid conversion is available on each channel. When several channels are enabled, ...
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AD7193 The AD7193 can be operated with CS used as a frame synchro- nization signal. This scheme is useful for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS because CS normally occurs after ...
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Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7193 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete low, the DOUT/ RDY line also goes ...
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AD7193 Continuous Read Rather than write to the communications register each time a conversion is complete to access the data, the AD7193 can be configured so that the conversions are placed on the DOUT/ RDY line automatically. By writing 01011100 ...
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RESET The circuitry and serial interface of the AD7193 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. This resets the logic, the digital filter, and the analog modulator, whereas ...
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AD7193 TEMPERATURE SENSOR Embedded in the AD7193 is a temperature sensor. This is selected using the TEMP bit in the configuration register. When the TEMP bit is set to 1, the temperature sensor is enabled. When the temperature sensor is ...
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The offset error is, typically, ±150 μV/gain. If the gain is changed advisable to perform a calibration. A zero-scale calibration (an internal zero-scale calibration or a system zero-scale calibration) reduces the offset error to the order of the ...
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AD7193 DIGITAL FILTER The AD7193 offers a lot of flexibility in the digital filter. The device has five filter options. The device can be operated with sinc or sinc filter, chop can be enabled or disabled, and ...
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When the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. When conversions are being performed on a single channel and a step change occurs on the analog input, the ...
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AD7193 Simultaneous 50 Hz/60 Hz rejection can also be achieved using the REJ60 bit in the mode register. When FS[9:0] is set to 96 and REJ60 is set to 1, notches are placed and 60 Hz. The ...
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Sinc Zero Latency Zero latency is enabled by setting the single bit (Bit 11) in the mode register to 1. With zero latency, the complete settling time is allowed for each conversion. Therefore, the conversion time when converting on ...
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AD7193 Simultaneous 50 Hz and 60 Hz rejection is obtained when FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in Figure 42. The output data rate when zero latency is disabled and 3.3 ...
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When a channel change occurs, the modulator and filter reset. The complete settling time is required to generate the first conversion after the channel change. Subsequent conversions on this channel occur at 1/f . ADC CHANNEL A CHANNEL CONVERSIONS CH ...
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AD7193 3 CHOP ENABLED (SINC FILTER) With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter ...
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The 50 Hz/60 Hz rejection can be improved by setting the REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and REJ60 set to 1, the filter response shown in Figure 53 is achieved. The output ...
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AD7193 4 50 Hz/60 Hz Rejection, Sinc Filter Figure 57 shows the frequency response when FS[9:0] is set to 6 and the postfilter averages by 16. This gives an output data rate of 42.10 Hz when the master clock equals ...
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FAST SETTLING MODE (SINC FILTER) In fast settling mode, the settling time is close to the inverse of the first filter notch. Therefore, the user can achieve 50 Hz and/ rejection at an output data rate close ...
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AD7193 Figure 65 shows the filter response when FS[9:0] is set to 5 and the post filter averages by 16. In this case, the output data rate is equal to 53.33 Hz when the first filter notch is placed at ...
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SUMMARY OF FILTER OPTIONS The AD7193 has several filter options. The filter that is chosen affects the output data rate, settling time, the rms noise, and the 50 Hz/60 Hz rejection. 1 Table 36. Filter Summary Filter FS[9: ...
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AD7193 GROUNDING AND LAYOUT Because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are common-mode voltages. The high common-mode rejection of the part removes common-mode noise on these inputs. The analog and ...
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APPLICATIONS INFORMATION The AD7193 provides a low cost, high resolution analog-to-digital function. Because the analog-to-digital function is provided by a Σ-Δ architecture, the part is more immune to noisy environments, making it ideal for use in sensor measurement and industrial ...
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... SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD7193BRUZ −40°C to +105°C AD7193BRUZ-REEL −40°C to +105°C AD7193BCPZ −40°C to +105°C AD7193BCPZ-RL −40°C to +105°C AD7193BCPZ-RL7 −40°C to +105° RoHS Compliant Part. 9.80 9.70 9. 4.50 4.40 4. 0.65 BSC 1 ...
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NOTES Rev Page AD7193 ...
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AD7193 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08367-0-4/10(B) Rev Page ...