AD7450ABRM Analog Devices Inc, AD7450ABRM Datasheet - Page 15

• Manufacturer Part Number: AD7450ABRM
• Description: 12-BIT Diff I/put, 1MSPS SAR ADC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7450ABRM

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 9.25mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-AD7450CBZ - BOARD EVALUATION FOR AD7450
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CIRCUIT INFORMATION
The AD7440/AD7450A are 10-bit and 12-bit fast, low power,
single-supply, successive approximation analog-to-digital
converters (ADCs). They can operate with a 5 V or 3 V power
supply and are capable of throughput rates up to 1 MSPS when
supplied with an 18 MHz SCLK. They require an external
reference to be applied to the V
reference chosen depending on the power supply and what suits
the application.
When they are operated with a 5 V supply, the maximum
reference that can be applied is 3.5 V. When they are operated
with a 3 V supply, the maximum reference that can be applied is
2.2 V (see the Reference section).
The AD7440/AD7450A have an on-chip differential track-and-
hold amplifier, a successive approximation (SAR) ADC, and a
serial interface housed in either an 8-lead SOT-23 or an MSOP
package. The serial clock input accesses data from the part and
provides the clock source for the successive approximation
ADC. The AD7440/AD7450A feature a power-down option for
reduced power consumption between conversions. The power-
down feature is implemented across the standard serial interface
as described in the Modes of Operation section.
CONVERTER OPERATION
The AD7440/AD7450A are successive approximation ADCs
based around two capacitive DACs. Figure 23 and Figure 24
show simplified schematics of the ADC in acquisition and
conversion phase, respectively. The ADC is comprised of
control logic, an SAR, and two capacitive DACs. In Figure 23
(acquisition phase), SW3 is closed, SW1 and SW2 are in
Position A, the comparator is held in a balanced condition,
and the sampling capacitor arrays acquire the differential
signal on the input.
V
V
IN+
IN–
B
A
A
B
V
REF
SW1
SW2
Figure 23. ADC Acquisition Phase
C
C
S
S
SW3
REF
COMPARATOR
pin, with the value of the
CAPACITIVE
CAPACITIVE
CONTROL
LOGIC
DAC
DAC
Rev. C | Page 15 of 28
When the ADC starts a conversion (Figure 24), SW3 opens and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistri-
bution DACs are used to add and subtract fixed amounts of
charge from the sampling capacitor arrays to bring the compar-
ator back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC’s output code. The output impedances of the
sources driving the V
otherwise, the two inputs have different settling times, resulting
in errors.
ADC TRANSFER FUNCTION
The output coding for the AD7440/AD7450A is twos
complement. The designed code transitions occur at successive
LSB values (1 LSB, 2 LSBs, and so on). The LSB size of the
AD7450A is 2 × V
2 × V
AD7440/AD7450A is shown in Figure 25.
V
V
IN+
IN–
REF
/1024. The ideal transfer characteristic of the
Figure 25. AD7440/AD7450A Ideal Transfer Characteristic
B
A
A
B
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
V
REF
SW1
SW2
Figure 24. ADC Conversion Phase
REF
–V
C
C
S
S
/4096, and the LSB size of the AD7440 is
REF
IN+
1 LSB
1LSB = 2
1LSB = 2
and the V
SW3
×
×
ANALOG INPUT
V
V
0 LSB
(V
REF
REF
COMPARATOR
IN+
IN–
/4096 AD7450A
/1024 AD7440
– V
AD7440/AD7450A
pins must be matched;
IN–
+V
)
REF
– 1 LSB
CAPACITIVE
CAPACITIVE
CONTROL
LOGIC
DAC
DAC