AD7782BRUZ-REEL Analog Devices Inc, AD7782BRUZ-REEL Datasheet - Page 9

• Manufacturer Part Number: AD7782BRUZ-REEL
• Description: 2 Chnl Non-writeable 24-bit ADC
• Manufacturer: Analog Devices Inc

Specifications of AD7782BRUZ-REEL

• Number Of Bits: 24
• Sampling Rate (per Second): 19.79
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 3.9mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bipolar Configuration/Output Coding
The analog inputs on the AD7782 accept bipolar input voltage
ranges. Signals on the AIN(+) input of the ADC are referenced
to the voltage on the respective AIN(–) input. For example, if
AIN(–) is 2.5 V and the AD7782 is configured for an analog input
range of ± 160 mV, the analog input range on the AIN(+) input
is 2.34 V to 2.66 V (i.e., 2.5 V ± 0.16 V).
The coding is offset binary with a negative full-scale voltage
resulting in a code of 000 . . . 000, a zero differential voltage
resulting in a code of 100 . . . 000, and a positive full-scale
voltage resulting in a code of 111 . . . 111. The output code for
any analog input voltage can be represented as follows:
Where AIN is the analog input voltage, GAIN is the PGA gain, i.e.,
1 on the ±2.56 V range and 16 on the ±160 mV range and N = 24.
Crystal Oscillator
The AD7782 is intended for use with a 32.768 kHz watch crystal.
A PLL internally locks onto a multiple of this frequency to provide
a stable 4.194304 MHz clock for the ADC. The modulator sample
rate is the same as the crystal oscillator frequency. The start-up
time associated with 32.768 kHz crystals is typically 300 ms. In
some cases, it will be necessary to connect capacitors on the crystal
to ensure that it does not oscillate at overtones of its fundamental
operating frequency. The values of capacitors will vary depending
on the manufacturer’s specifications.
Reference Input
The AD7782 has a fully-differential reference input capability
for the channel. The common-mode range for these differential
inputs is from GND to V
therefore excessive R-C source impedances will introduce gain
errors. The reference voltage REFIN (REFIN(+) – REFIN(–)) is
2.5 V nominal for specified operation but the AD7782 is functional
with reference voltages from 1 V to V
excitation (voltage or current) for the transducer on the analog
input also drives the reference voltage for the part, the effect of the
low frequency noise in the excitation source will be removed as the
application is ratiometric. If the AD7782 is used in a nonratiometric
application, a low noise reference should be used. Recommended
reference voltage sources for the AD7782 include the AD780,
REF43, and REF192. It should also be noted that the reference
inputs provide a high impedance, dynamic load. Because the input
impedance of each reference input is dynamic, resistor/capacitor
combinations on these inputs can cause dc gain errors, depending
on the output impedance of the source that is driving the reference
inputs. Reference voltage sources like those recommended above
(e.g., AD780) will typically have low output impedances and are
therefore tolerant to having decoupling capacitors on the REFIN(+)
Code
=
2
N
−
1
×
[
(
AIN
DD
. The reference input is unbuffered and
×
GAIN
DD
/ .
. In applications where the
(
1 024
×
V
REF
)
)
+
1
]
without introducing gain errors in the system. Deriving the refer-
ence input voltage across an external resistor will mean that the
reference input sees a significant external source impedance. Exter-
nal decoupling on the REFIN pins would not be recommended in
this type of circuit configuration.
Grounding and Layout
Since the analog inputs and reference inputs on the ADC are
differential, most of the voltages in the analog modulator are common-
mode voltages. The excellent common-mode rejection of the part
will remove common-mode noise on these inputs. The digital filter
will provide rejection of broadband noise on the power supply,
except at integer multiples of the modulator sampling frequency.
The digital filter also removes noise from the analog and reference
inputs provided these noise sources do not saturate the analog
modulator. As a result, the AD7782 is more immune to noise inter-
ference than a conventional high-resolution converter. However,
because the resolution of the AD7782 is so high, and the noise
levels from the AD7782 so low, care must be taken with regard to
grounding and layout.
The printed circuit board that houses the AD7782 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. A minimum etch tech-
nique is generally best for ground planes as it gives the best shielding.
It is recommended that the AD7782’s GND pin be tied to the
AGND plane of the system. In any layout, it is important that the
user keep in mind the flow of currents in the system, ensuring
that the return paths for all currents are as close as possible to the
paths the currents took to reach their destinations. Avoid forcing
digital currents to flow through the AGND sections of the layout.
The AD7782’s ground plane should be allowed to run under the
AD7782 to prevent noise coupling. The power supply lines to the
AD7782 should use as wide a trace as possible to provide low imped-
ance paths and reduce the effects of glitches on the power supply
line. Fast switching signals like clocks should be shielded with digital
ground to avoid radiating noise to other sections of the board, and
clock signals should never be run near the analog inputs. Avoid
crossover of digital and analog signals. Traces on opposite sides of
the board should run at right angles to each other. This will reduce the
effects of feedthrough through the board. A microstrip technique
is by far the best, but is not always possible with a double-sided
board. In this technique, the component side of the board is dedi-
cated to ground planes while signals are placed on the solder side.
Good decoupling is important when using high-resolution ADCs.
VDD should be decoupled with 10 µF tantalum in parallel with
0.1 µF capacitors to GND. To achieve the best from these decoupling
components, they have to be placed as close as possible to the
device, ideally right up against the device. All logic chips should
be decoupled with 0.1 µF ceramic capacitors to DGND.
AD7782