AD8138AR Analog Devices Inc, AD8138AR Datasheet - Page 21

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AD8138AR

Manufacturer Part Number
AD8138AR
Description
IC,Differential Amplifier,BIPOLAR,SOP,8PIN,PLASTIC
Manufacturer
Analog Devices Inc
Type
ADC Driverr
Datasheet

Specifications of AD8138AR

Rohs Status
RoHS non-compliant
Design Resources
DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7352 (CN0040) DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7356 (CN0041) DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7357 (CN0061)
Applications
Data Acquisition
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status

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HIGH PERFORMANCE ADC DRIVING
The circuit in Figure 46 shows a simplified front-end
connection for an AD8138 driving an AD9224, a 12-bit,
40 MSPS ADC. The ADC works best when driven differentially,
which minimizes its distortion. The AD8138 eliminates the
need for a transformer to drive the ADC and performs single-
ended-to-differential conversion, common-mode level-shifting,
and buffering of the driving signal.
The positive and negative outputs of the AD8138 are connected
to the respective differential inputs of the
49.9 Ω resistors to minimize the effects of the switched-capacitor
front end of the AD9224. For best distortion performance, it
runs from supplies of ±5 V.
The AD8138 is configured with unity gain for a single-ended,
input-to-differential output. The additional 23 Ω, 523 Ω total, at
the input to −IN is to balance the parallel impedance of the
50 Ω source and its 50 Ω termination that drives the
noninverting input.
SOURCE
50Ω
49.9Ω
0.1pF
499Ω
AD9224
523Ω
Figure 46. AD8138 Driving an AD9224, a 12-Bit, 40 MSPS ADC
8
2
1
via a pair of
+
AD8138
+5V
–5V
V
3
6
OCM
499Ω
499Ω
5
4
Rev. F | Page 21 of 24
49.9Ω
49.9Ω
The signal generator has a ground-referenced, bipolar output,
that is, it drives symmetrically above and below ground.
Connecting V
common-mode of the AD8138 at 2.5 V, which is the midsupply
level for the AD9224. This voltage is bypassed by a 0.1 μF
capacitor.
The full-scale analog input range of the
4 V p-p, by shorting the SENSE terminal to AVSS. This has
been determined to be the scaling to provide minimum
harmonic distortion.
For the AD8138 to swing at 4 V p-p, each output swings 2 V p-p
while providing signals that are 180° out of phase. With a
common-mode voltage at the output of 2.5 V, each AD8138
output swings between 1.5 V and 3.5 V.
A ground-referenced 4 V p-p, 5 MHz signal at D
test the circuit in Figure 46. When the combined-device circuit
was run with a sampling rate of 20 MSPS, the spurious-free
dynamic range (SFDR) was measured at −85 dBc.
24
23
VINB
VINA
0.1pF
AVSS
AVDD
15 26
16 25
OCM
+5V
AD9224
DRVDD
SENSE
to the CML pin of the
28
17
0.1pF
CML
22
DRVSS
27
DIGITAL
OUTPUTS
AD9224
AD9224
IN
is set to
sets the output
+ was used to
AD8138

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