AD9251BCPZ-40 Analog Devices Inc, AD9251BCPZ-40 Datasheet
AD9251BCPZ-40
Specifications of AD9251BCPZ-40
Related parts for AD9251BCPZ-40
AD9251BCPZ-40 Summary of contents
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FEATURES 1.8 V analog supply operation 1 3.3 V output supply SNR 74.3 dBFS at 9.7 MHz input 71.5 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input 80 dBc at 200 MHz input Low ...
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AD9251 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ...
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GENERAL DESCRIPTION The AD9251 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and- hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with ...
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AD9251 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 1. Parameter Temp RESOLUTION Full ACCURACY ...
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AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR ...
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AD9251 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) ...
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SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate ...
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AD9251 TIMING SPECIFICATIONS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time SSYNC t SYNC to rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and ...
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CLK SSYNC HSYNC SYNC Figure 4. SYNC Input Timing Requirements Rev Page AD9251 ...
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AD9251 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to AGND DRVDD to AGND VIN+A, VIN+B, VIN−A, VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS (LSB) D0B DRVDD NOTES CONNECT 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Table 8. Pin Function Description ...
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AD9251 Pin No. Mnemonic 55 VREF 56 SENSE 57 VCM 58 RBIAS 61, 62 VIN−B, VIN+B Description Voltage Reference Input/Output. Reference Mode Selection. Analog output voltage at midsupply to set common mode of the analog inputs. Sets Analog Current Bias. ...
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TYPICAL PERFORMANCE CHARACTERISTICS AD9251-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 80MSPS 9.7MHz @ –1dBFS –15 SNR ...
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AD9251 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 100 SFDR (dBc SNR (dBFS ...
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AD9251-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 65MSPS 9.7MHz @ –1dBFS –15 SNR = 73.5dB (74.5dBFS) ...
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AD9251 AD9251-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 40MSPS 9.7MHz @ –1dBFS –15 SNR = 73.5dB ...
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AD9251-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 20MSPS 9.7MHz @ –1dBFS –15 SNR = 73.5dBFS (74.5dBFS) ...
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AD9251 EQUIVALENT CIRCUITS AVDD VIN±x Figure 29. Equivalent Analog Input Circuit 5Ω CLK+ 15kΩ 15kΩ 5Ω CLK– Figure 30. Equivalent Clock Input Circuit AVDD DRVDD 30kΩ 350Ω SDIO/DCS 30kΩ Figure 31. Equivalent SDIO/DCS Input Circuit 0.9V Figure 33. Equivalent SCLK/DFS, ...
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DRVDD AVDD 30kΩ 350Ω CSB Figure 35. Equivalent CSB Input Circuit AVDD 375Ω SENSE Figure 36. Equivalent SENSE Circuit VREF Figure 37. Equivalent VREF Circuit Rev Page AD9251 AVDD 375Ω 7.5kΩ ...
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AD9251 THEORY OF OPERATION The AD9251 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent ...
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Input Common Mode The analog inputs of the AD9251 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide a dc bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the ...
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AD9251 Single-Ended Input Configuration A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common- mode swing. If the source impedances on each input are matched, there ...
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VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD9251. The VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are ...
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AD9251 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac- teristics. Figure 48 shows the typical drift characteristics of the internal reference in 1.0 ...
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If a low jitter clock source is not available, another option couple a differential PECL signal to the sample clock input pins, as shown in Figure 52. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 excellent jitter performance. 0.1µF CLOCK INPUT AD951x ...
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AD9251 Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low fre- quency SNR (SNR ) at a given input frequency (f LF jitter (t ) can ...
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DIGITAL OUTPUTS The AD9251 output drivers can be configured to interface with 1 3.3 V CMOS logic families. Output data can also be multiplexed onto a single output bus to reduce the total number of traces required. The ...
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AD9251 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9251 includes a built-in test feature designed to enable verification of the integrity of each channel, as well as to facilitate board level debugging. A built-in self-test (BIST) feature that verifies the ...
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SERIAL PORT INTERFACE (SPI) The AD9251 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, ...
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AD9251 HARDWARE INTERFACE The pins described in Table 13 constitute the physical interface between the programming device of the user and the serial port of the AD9251. The SCLK pin and the CSB pin function as inputs when using the ...
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MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table (see Table 16) has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address ...
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AD9251 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 16 are not currently supported for this device. Table 16. Address Register Bit 7 (Hex) Name (MSB) Chip Configuration Registers 0x00 SPI port 0 ...
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Address Register Bit 7 (Hex) Name (MSB) 0x0D Test mode (local) User test mode (local single 01 = alternate 10 = single once 11 = alternate once 0x0E BIST enable Open 0x10 Offset adjust 8-bit device offset adjustment ...
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AD9251 Address Register Bit 7 (Hex) Name (MSB) 0x2A Features Open 0x2E Output assign Open Digital Feature Control 0x100 Sync control Open (global) 0x101 USR2 Enable OEB Pin 47 (local) MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled ...
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APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9251 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power ...
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... AD9251BCPZRL7-80 –40°C to +85° AD9251BCPZ-65 –40°C to +85° AD9251BCPZRL7-65 –40°C to +85° AD9251BCPZ-40 –40°C to +85° AD9251BCPZRL7-40 –40°C to +85° AD9251BCPZ-20 –40°C to +85° AD9251BCPZRL7-20 –40°C to +85°C 1 AD9251-80EBZ ...