AD9398KSTZ-150 Analog Devices Inc, AD9398KSTZ-150 Datasheet

IC,TV/VIDEO CIRCUIT,Video Interface Circuit,CMOS,QFP,100PIN,PLASTIC

AD9398KSTZ-150

Manufacturer Part Number
AD9398KSTZ-150
Description
IC,TV/VIDEO CIRCUIT,Video Interface Circuit,CMOS,QFP,100PIN,PLASTIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9398KSTZ-150

Applications
Video
Interface
HDMI
Voltage - Supply
3.15 V ~ 3.47 V
Package / Case
100-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9398/PCBZ - BOARD EVALUATION FOR AD9398
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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FEATURES
HDMI interface
Digital video interface
Digital audio interface
APPLICATIONS
Advanced TVs
HDTVs
Projectors
LCD monitors
GENERAL DESCRIPTION
The AD9398 offers a high definition multimedia interface
(HDMI) receiver integrated on a single chip. Also included is
support for high bandwidth digital content protection (HDCP).
The AD9398 contains a HDMI 1.0-compatible receiver and
supports all HDTV formats (up to 1080p) and display resolu-
tions up to SXGA (1280 × 1024 @ 75 Hz). The receiver features
an intrapair skew tolerance of up to one full clock cycle. With
the inclusion of HDCP, displays can now receive encrypted
video content. The AD9398 allows for authentication of a video
receiver, decryption of encoded data at the receiver, and
renewability of that authentication during transmission as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9398 is
provided in a space-saving 100-lead, surface-mount, Pb-free,
plastic LQFP and is specified over the 0°C to 70°C temperature
range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
(HDCP 1.1)
Multichannel I
Supports high bandwidth digital content protection
RGB to YCbCr 2-way color conversion
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
HDMI 1.1, DVI 1.0
150 MHz HDMI receiver
Supports high bandwidth digital content protection
HDMI 1.1-compatible audio interface
SPDIF (IEC90658-compatible) digital audio output
2
S audio output (up to 8 channels)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
DDCSDA
DDCSCL
RTERM
RxC+
RxC–
Rx0+
Rx1+
Rx2+
Rx0–
Rx1–
Rx2–
MDA
SDA
MCL
SCL
HDMI™ Display Interface
FUNCTIONAL BLOCK DIAGRAM
POWER MANAGEMENT
SERIAL REGISTER
RECEIVER
HDCP
HDMI
AND
© 2005 Analog Devices, Inc. All rights reserved.
Figure 1.
2
R/G/B 8 × 3
OR YCbCr
DATACK
HSYNC
VSYNC
DE
AD9398
AD9398
www.analog.com
R/G/B 8 × 3
YCbCr (4:2:2
OR 4:4:4)
2
S/PDIF OUT
8-CHANNEL
I
MCLK
LRCLK
2
S
DATACK
HSOUT
VSOUT
DE

Related parts for AD9398KSTZ-150

AD9398KSTZ-150 Summary of contents

Page 1

FEATURES HDMI interface Supports high bandwidth digital content protection RGB to YCbCr 2-way color conversion 1.8 V/3.3 V power supply 100-lead, Pb-free LQFP RGB and YCbCr output formats Digital video interface HDMI 1.1, DVI 1.0 150 MHz HDMI receiver Supports ...

Page 2

AD9398 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Digital Interface Electrical Characteristics ............................... 3 Absolute Maximum Ratings............................................................ 5 Explanation of Test Levels ........................................................... 5 ESD ...

Page 3

... Output drive = low IV Output drive = high IV Output drive = low IV 75 Rev Page AD9398KSTZ-150 Max Min Typ Max 2.6 0.8 0.8 − − 0.1 DD 0.4 0 Binary 35 AD9398KSTZ-100 AD9398KSTZ-150 Typ Max Min Typ 8 8 2.5 0.8 − 0.1 − 0.1 0 700 75 AD9398 Unit ...

Page 4

... Output drive = high Output drive = low Output drive = high Output drive = low −0 Rev Page AD9398KSTZ-100 AD9398KSTZ-150 Typ Max Min Typ 3.3 3.47 3.15 3.3 3.3 347 1.7 3.3 1.8 1.9 1.7 1.8 1.8 1.9 1.7 1.8 80 100 80 40 100 3 55 ...

Page 5

ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Analog Inputs Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. ...

Page 6

AD9398 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 GREEN 7 2 GREEN 6 3 GREEN 5 4 GREEN 4 5 GREEN 3 6 GREEN 2 7 GREEN 1 8 GREEN GND 11 BLUE 7 12 ...

Page 7

Pin Type Pin No. POWER SUPPLY 80, 76, 72, 67, 45, 33 100, 90, 10 59, 56, 54 48, 32, 30 CONTROL 83 82 HDCP AUDIO DATA OUTPUTS ...

Page 8

AD9398 Mnemonic Description RTERM RTERM is the termination resistor used to drive the AD9398 internally to a precise 50 Ω termination for TMDS lines. This should be a 500 Ω 1% tolerance resistor. AUDIO DATA OUTPUT S/PDIF Sony/Philips Digital Interface. ...

Page 9

DESIGN GUIDE GENERAL DESCRIPTION The AD9398 is a fully integrated solution for receiving DVI/HDMI signals and is capable of decoding HDCP- encrypted signals through connections to an external EEPROM. The circuit is ideal for providing an interface for HDTV monitors ...

Page 10

AD9398 TIMING The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally. Figure 3 shows the timing operation of the AD9398. t PER ...

Page 11

TO 4:2:2 FILTER The AD9398 contains a filter that allows it to convert a signal from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the maximum accuracy and fidelity of the original signal. Input Color Space to Output Color Space ...

Page 12

AD9398 AUDIO PLL SETUP Data contained in the audio infoframes, among other registers, define for the AD9398 HDMI receiver not only the type of audio, but the sampling frequency (f ). The audio infoframe also S contains information about the ...

Page 13

AUDIO BOARD LEVEL MUTING The audio can be muted through the infoframes or locally via the serial bus registers. This can be controlled with Register R0x57, Bits [7:4]. AVI Infoframes The HDMI TMDS transmission contains infoframes with specific information for ...

Page 14

AD9398 2-WIRE SERIAL REGISTER MAP The AD9398 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table ...

Page 15

Read/Write or Read Hex Address Only Bits [5] [4] [0] 0x25 Read/Write [7:6] [5:4] [3:2] [1] [0] 0x26 Read/Write [7] [5] [4] [3] [2:1] [0] 0x27 Read/Write [7] [6] [5] Default Value Register Name **1***** DE Output Polarity ***1**** Field ...

Page 16

AD9398 Read/Write or Read Hex Address Only Bits [4] [3] [2:0] 0x28 Read/Write [7:2] [1:0] 0x29 Read/Write [7:0] 0x2A Read/Write [3:0] 0x2B Read/Write [7:0] 0x2C Read/Write [3:0] 0x2D Read/Write [7:0] 0x2E Read/Write [7] [6:5] [4:0] 0x2F Read [6] [5] [4] ...

Page 17

Read/Write or Read Hex Address Only Bits [5] [4] [3] [2] [1] 0x35 Read/Write [6:5] [4:0] 0x36 Read/Write [7:0] 0x37 Read/Write [4:0] 0x38 Read/Write [7:0] 0x39 Read/Write [4:0] 0x3A Read/Write [7:0] 0x3B Read/Write [4:0] 0x3C Read/Write [7:0] 0x3D Read/Write [4:0] ...

Page 18

AD9398 Read/Write or Read Hex Address Only Bits 0x44 Read/Write [7:0] 0x45 Read/Write [4:0] 0x46 Read/Write [7:0] 0x47 Read/Write [4:0] 0x48 Read/Write [7:0] 0x49 Read/Write [4:0] 0x4A Read/Write [7:0] 0x4B Read/Write [4:0] 0x4C Read/Write [7:0] 0x50 Read/Write [7:0] 0x56 Read/Write ...

Page 19

Read/Write or Read Hex Address Only Bits 0x5B Read [3] 0x5E Read [7:6] [5: 0x5F Read [7:0] 0x60 Read [7:4] [3:0] 0x61 Read [5:4] [3:0] 0x62 Read [3:0] 0x7B Read [7:0] 0x7C Read [7:0] 0x7D Read [7:4] ...

Page 20

AD9398 Read/Write or Read Hex Address Only Bits 0x7F Read [7:0] 0x80 Read [7:0] 0x81 Read [6:5] 4 [3:2] [1:0] 0x82 Read [7:6] [5:4] [3:0] 0x83 Read [1:0] 0x84 Read [6:0] 0x85 Read [3:0] 0x86 Read [7:0] Default Value Register ...

Page 21

Read/Write or Read Hex Address Only Bits 0x87 Read [6:0] 0x88 Read [7:0] 0x89 Read [7:0] 0x8A Read [7:0] 0x8B Read [7:0] 0x8C Read [7:0] 0x8D Read [7:0] 0x8E Read [7:0] 0x8F Read [6:0] 0x90 Read [7:0] 0x91 Read [7:4] ...

Page 22

AD9398 Read/Write or Read Hex Address Only Bits [1:0] 0x93 Read [7:0] 0x94 Read [7:0] 7 0x95 Read [6:3] 0x96 Read [7:0] 0x97 Read [6:0] 0x98 Read [7:0] 0x99 Read [7:0] 0x9A Read [7:0] 0x9B Read [7:0] 0x9C Read [7:0] ...

Page 23

Read/Write or Read Hex Address Only Bits 0xAF Read [6:0] 0xB0 Read [7:0] 0xB1 Read [7:0] 0xB2 Read [7:0] 0xB3 Read [7:0] 0xB4 Read [7:0] 0xB7 Read [6:0] 0xB8 Read [7:0] 0xB9 Read [7:0] 0xBA Read [7:0] 0xBB Read [7:0] ...

Page 24

AD9398 Read/Write or Read Hex Address Only Bits 0xC8 7 Read 6 [2:0] 0xC9 Read [7:0] 0xCA Read [7:0] 0xCB Read [7:0] 0xCC Read [7:0] 0xCD Read [7:0] 0xCE Read [7:0] 0xCF Read [6:0] 0xD0 Read [7:0] 0xD1 Read [7:0] ...

Page 25

SERIAL CONTROL REGISTER DETAILS CHIP IDENTIFICATION 0x00—Bits[7:0] Chip Revision An 8-bit value that reflects the current chip revision. 0x11—Bit[7] HSYNC Source 0 = HSYNC SOG. The power-up default is 0. These selections are ignored if Register 0x11, ...

Page 26

AD9398 0x23—Bits[7:0] HSYNC Duration An 8-bit register that sets the duration of the HSYNC output pulse. The leading edge of the HSYNC output is triggered by the internally generated, phase-adjusted PLL feedback clock. The AD9398 then counts a number of ...

Page 27

Output Three-State When enabled, this bit puts all outputs (except SOGOUT high impedance state normal outputs all outputs (except SOGOUT) in high impedance mode. The power-up default setting is 0. 0x26—Bit[5] S/PDIF Three-State ...

Page 28

AD9398 0x2E—Bit[7] Ctrl Enable When set, this bit allows Ctrl [3:0] signals decoded from the 2 DVI to be output on the I S data pins lines Ctrl[3:0] output lines. The ...

Page 29

Macrovision Detect Mode 0 = standard definition progressive scan mode. 0x33—Bit[6] Macrovision Settings Override This defines whether preset values are used for the MV line counts and pulse widths or the values stored ...

Page 30

AD9398 0x40—Bits[7:0] CSC B2 LSBs 0x41—Bits[4:0] CSC B3 MSBs The default value for the 13-bit B3 is 0x1E89. 0x42—Bits[7:0] CSC B3 LSBs 0x43—Bits[4:0] CSC B4 MSBs The default value for the 13-bit B4 is 0x0291. 0x44—Bits[7:0] CSC B4 LSBs 0x45—Bits[4:0] ...

Page 31

Channel Status Mode 0x5E—Bits[5:3] PCM Audio Data 0x5E—Bit[2] Copyright Information 0x5E—Bit[1] Linear PCM Identification 0x5E—Bit[0] Use of Channel Status Block 0x5F—Bits[7:0] Channel Status Category Code 0x60—Bits[7:4] Channel Number 0x60—Bits[3:0] Source Number 0x61—Bits[5:4] Clock Accuracy 0x61—Bits[3:0] Sampling Frequency Table 21. ...

Page 32

AD9398 0x87—Bit[6:0] New Data Flags (NDF) This register indicates whether data in specific sections has changed. In the address space from 0x80 to 0xFF, each register address ending in 0b111 (for example, 0x87, 0x8F, 0x97, 0xAF NDF register. ...

Page 33

Table 33. CA Bit 4 Bit 3 Bit 2 Bit 1 Bit ...

Page 34

AD9398 0xA3—Bits[7:0] PD2 0xA4—Bits[7:0] PD3 0xA5—Bits[7:0] PD4 0xA6—Bits[7:0] PD5 0xA7—Bits[6:0] New Data Flags See Register 0x87 for a description. 0xA8—Bits[7:0] PD6 0xA9—Bits[7:0] PD7 0xAA—Bits[7:0] PD8 0xAB—Bits[7:0] PD9 0xAC—Bits[7:0] PD10 0xAD—Bits[7:0] PD11 0xAE—Bits[7:0] PD12 0xAF—Bits[6:0] New Data Flags See Register 0x87 ...

Page 35

ISRC1 Packet Byte 0 (ISRC1_PB0) 0xCA—Bits[7:0] ISRC1_PB1 0xCB—Bits[7:0] ISRC1_PB2 0xCC—Bits[7:0] ISRC1_PB3 0xCD—Bits[7:0] ISRC1_PB4 0xCE—Bits[7:0] ISRC1_PB5 0xCF—Bits[6:0] New Data Flags See Register 0x87 for a description. 0xD0—Bits[7:0] ISRC1_PB6 0xD1—Bits[7:0] ISRC1_PB7 0xD2—Bits[7:0] ISRC1_PB8 0xD3—Bits[7:0] ISRC1_PB9 0xD4—Bits[7:0] ISRC1_PB10 0xD5—Bits[7:0] ISRC1_PB11 0xD6—Bits[7:0] ISRC1_PB12 ...

Page 36

AD9398 2-WIRE SERIAL CONTROL PORT A 2-wire serial interface control interface is provided in the AD9398 two AD9398 devices can be connected to the 2-wire serial interface, with a unique address for each device. The 2-wire serial interface ...

Page 37

SERIAL INTERFACE READ/WRITE EXAMPLES Write to one control register: • Start signal • Slave address byte (R/ W bit = low) • Base address byte • Data byte to base address • Stop signal Write to four consecutive control registers: ...

Page 38

AD9398 PCB LAYOUT RECOMMENDATIONS The AD9398 is a high precision, high speed digital device. To achieve the maximum performance from the part impor- tant to have a well designed board. The following is a guide for designing a ...

Page 39

COLOR SPACE CONVERTER (CSC) COMMON SETTINGS Table 38. HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting for AD9398) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x0C 0x52 Register Green/Y Coeff 1 Address 0x3D 0x3E Value ...

Page 40

AD9398 Table 42. RGB (0 to 255) to HDTV YCrCb (0 to 255) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x08 0x2D Register Green/Y Coeff 1 Address 0x3D 0x3E Value 0x03 0x68 Register Blue/Cb Coeff 1 Address 0x45 0x46 ...

Page 41

... SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Max Speed (MHz) Model Analog Digital AD9398KSTZ-100 1 100 100 AD9398KSTZ-150 150 150 AD9398/PCB Pb-free part. 1.60 MAX 0.75 100 1 0.60 0.45 PIN 1 TOP VIEW (PINS DOWN) 0.20 0.09 7° ...

Page 42

AD9398 NOTES Rev Page ...

Page 43

NOTES Rev Page AD9398 ...

Page 44

AD9398 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05678-0-10/05(0) Rev Page ...

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