AD9513/PCBZ Analog Devices Inc, AD9513/PCBZ Datasheet

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AD9513/PCBZ

Manufacturer Part Number
AD9513/PCBZ
Description
800MHz 3-Chan Clock Distribution EB
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9513/PCBZ

Main Purpose
Timing, Clock Distribution
Utilized Ic / Part
AD9513
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FEATURES
1.6 GHz differential clock input
3 programmable dividers
Three 800 MHz/250 MHz LVDS/CMOS clock outputs
Device configured with 4-level logic pins
Space-saving, 32-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
ATE
GENERAL DESCRIPTION
The AD9513 features a three-output clock distribution IC in a
design that emphasizes low jitter and phase noise to maximize
data converter performance. Other applications with
demanding phase noise and jitter requirements also benefit
from this part.
There are three independent clock outputs that can be set to
either LVDS or CMOS levels. These outputs operate to
800 MHz in LVDS mode and to 250 MHz in CMOS mode.
Each output has a programmable divider that can be set to
divide by a selected set of integers ranging from 1 to 32. The
phase of one clock output relative to the other clock output can
be set by means of a divider phase select function that serves as
a coarse timing adjustment.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Divide-by in range from1 to 32
Phase select for coarse delay adjust
Additive output jitter 300 fs rms
Time delays up to 11.6 ns
800 MHz Clock Distribution IC, Dividers,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
SYNCB
One of the outputs features a delay element with three selectable
full-scale delay values (1.8 ns, 6.0 ns, and 11.6 ns), each with
16 steps of fine adjustment.
The AD9513 does not require an external controller for
operation or setup. The device is programmed by means of
11 pins (S0 to S10) using 4-level logic. The programming pins
are internally biased to ⅓ V
⅔ V
The AD9513 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9513 is available in a 32-lead LFCSP and operates from
a single 3.3 V supply. The temperature range is −40°C to +85°C.
CLKB
CLK
S
. V
Delay Adjust, Three Outputs
VREF
S
(3.3 V) and GND (0 V) provide the other two logic levels.
FUNCTIONAL BLOCK DIAGRAM
RSET
S10 S9
VS
S8
© 2005 Analog Devices, Inc. All rights reserved.
/1. . . /32
/1. . . /32
/1. . . /32
S7
S
. The VREF pin provides a level of
Figure 1.
GND
SETUP LOGIC
S6
S5
AD9513
S4
t
S3
S2
AD9513
LVDS/CMOS
LVDS/CMOS
LVDS/CMOS
www.analog.com
S1
S0
OUT0
OUT0B
OUT1
OUT1B
OUT2
OUT2B

Related parts for AD9513/PCBZ

AD9513/PCBZ Summary of contents

Page 1

FEATURES 1.6 GHz differential clock input 3 programmable dividers Divide-by in range from1 to 32 Phase select for coarse delay adjust Three 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter 300 fs rms Time delays up to 11.6 ns ...

Page 2

AD9513 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Clock Input.................................................................................... 3 Clock Outputs ............................................................................... 3 Timing Characteristics ................................................................ 4 Clock Output Phase Noise .......................................................... 6 Clock Output Additive ...

Page 3

SPECIFICATIONS Typical (typ) is given for V = 3.3 V ± 5 values are given over full V and T (−40°C to +85°C) variation CLOCK INPUT Table 1. Parameter CLOCK INPUT (CLK) Input Frequency 1 Input ...

Page 4

AD9513 TIMING CHARACTERISTICS CLK input slew rate = 1 V/ns or greater. Table 3. Parameter LVDS Output Rise Time Output Fall Time PROPAGATION DELAY CLK-TO-LVDS OUT LVDS OUT0, OUT1, OUT2 Divide = 1 Divide ...

Page 5

Parameter Zero-Scale Delay Time Zero-Scale Variation with Temperature 3 Full-Scale Time Delay Full-Scale Variation with Temperature Linearity, DNL Linearity, INL 1 This is the difference between any two similar delay paths within a single device operating ...

Page 6

AD9513 CLOCK OUTPUT PHASE NOISE Table 4. Parameter CLK-TO-LVDS ADDITIVE PHASE NOISE CLK = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset ...

Page 7

Parameter CLK = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset ...

Page 8

AD9513 CLOCK OUTPUT ADDITIVE TIME JITTER Table 5. Parameter LVDS OUTPUT ADDITIVE TIME JITTER CLK= 400 MHz LVDS (OUT0) = 100 MHz Divide Ratio = 4 LVDS (OUT1, OUT2) = 100 MHz CLK = 400 MHz LVDS (OUT0) = 100 ...

Page 9

Parameter 1 DELAY BLOCK ADDITIVE TIME JITTER Delay FS = 1.8 ns Fine Adj. 00000 Delay FS = 1.8 ns Fine Adj. 11111 Delay FS = 6.0 ns Fine Adj. 00000 Delay FS = 6.0 ns Fine Adj. 11111 Delay ...

Page 10

AD9513 TIMING DIAGRAMS t CLK CLK t LVDS t CMOS Figure 2. CLK/CLKB to Clock Output Timing, DIV = 1 Mode DIFFERENTIAL 80% LVDS 20 Figure 3. LVDS Timing, Differential SINGLE-ENDED 20 Rev Page ...

Page 11

ABSOLUTE MAXIMUM RATINGS Table 8. With Respect to Parameter or Pin VS GND RSET GND CLK GND CLK CLKB OUT0, OUT1, OUT2 GND FUNCTION GND STATUS GND 1 Junction Temperature Storage Temperature Lead Temperature (10 sec) ESD CAUTION ESD (electrostatic ...

Page 12

AD9513 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VS 1 CLK 2 CLKB 3 AD9513 VS 4 TOP VIEW SYNCB 5 (Not to Scale) VREF 6 S10 Figure 5. 32-Lead LFCSP Pin Configuration Note that the exposed paddle on ...

Page 13

TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 degrees for each cycle. Actual signals, however, display a certain amount ...

Page 14

AD9513 TYPICAL PERFORMANCE CHARACTERISTICS 0.4 3 LVDS (DIV ON) 0.3 3 LVDS (DIV = 1) 0.2 0.1 200 400 OUTPUT FREQUENCY (MHz) Figure 7. Power vs. Frequency—LVDS START 300kHz STOP 5GHz Figure 8. CLK Smith Chart (Evaluation Board) 0.7 0.6 ...

Page 15

VERT 100mV/DIV Figure 10. LVDS Differential Output @ 800 MHz VERT 500mV/DIV Figure 11. CMOS Single-Ended Output @ 250 MHz with 10 pF Load 750 700 650 600 550 500 100 HORIZ 500ps/DIV Figure 12. LVDS Differential Output Swing vs. ...

Page 16

AD9513 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k OFFSET (Hz) Figure 14. Additive Phase Noise—LVDS DIV 1, 245.76 MHz –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k OFFSET (Hz) ...

Page 17

FUNCTIONAL DESCRIPTION OVERALL The AD9513 provides for the distribution of its input clock three outputs. Each output can be set to either LVDS or CMOS logic levels. Each output has its own divider that can be set ...

Page 18

AD9513 Synchronization is initiated by pulling the SYNCB pin low for a minimum of 5 ns. The input clock does not have to be present at the time the command is issued. The synchronization occurs after four input clock cycles. ...

Page 19

Table 11. Output Delay Full Scale S0 Delay 0 Bypass 1/3 1.8 ns 2/3 6 11.6 ns Table 12. Output Logic Configuration S1 S2 OUT0 OUT1 0 0 OFF LVDS 1/3 0 CMOS CMOS 2/3 0 LVDS LVDS ...

Page 20

AD9513 Table 16. OUT0 Divide or OUT2 Divide OUT0 1 Divide (Duty Cycle S9 S10 S2 ≠ (50%) 2 (33 (50%) 0 1/3 5 (40%) 1/3 1/3 6 ...

Page 21

DELAY BLOCK OUT2 includes an analog delay element that gives variable time delays (ΔT) in the clock signal passing through that output. CLOCK INPUT OUT1 ONLY ÷N ØSELECT ∆T FINE DELAY ADJUST (16 STEPS) FULL SCALE : 1.5ns, 5ns, 10ns ...

Page 22

AD9513 POWER SUPPLY The AD9513 requires a 3.3 V ± 5% power supply for V tables in the Specifications section give the performance expected from the AD9513 with the power supply voltage within this range case should the ...

Page 23

APPLICATIONS USING THE AD9513 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed, analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought sampling mixer; any ...

Page 24

AD9513 Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9513 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown ...

Page 25

PHASE NOISE AND JITTER MEASUREMENT SETUPS WENZEL EVALUATION BOARD OSCILLATOR SPLITTER 0° ZESC-2-11 EVALUATION BOARD WENZEL OSCILLATOR ⎡ V ⎢ A_RMS ⎢ ⎣ J_RMS where the rms time jitter. j_RMS SNR is the signal-to-noise ratio. ...

Page 26

AD9513 OUTLINE DIMENSIONS BSC SQ PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9513BCPZ −40°C to +85°C 1 AD9513BCPZ-REEL7 −40°C to +85°C AD9513/PCB Pb-free part. 5.00 0.60 MAX 0.50 ...

Page 27

NOTES Rev Page AD9513 ...

Page 28

AD9513 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05595–0–9/05(0) Rev Page ...

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