AD9520-2BCPZ Analog Devices Inc, AD9520-2BCPZ Datasheet

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... GHz. An external 3.3 V/5 V VCO/VCXO 2.4 GHz can also be used. 1 The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-2 is used referring to that specific member of the AD9520 family. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use ...

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... AD9520-2 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 7 Clock Outputs ............................................................................... 7 Timing Characteristics ................................................................ 8 Timing Diagrams ..................................................................... 9 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ............................................................ 10 Clock Output Absolute Phase Noise (Internal VCO Used Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO) ...

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... End-of-Data (Operational Code 0xFF) ............................... 59 Pseudo-End-of-Data (Operational Code 0xFE) ................. 59 Thermal Performance ..................................................................... 61 Register Map .................................................................................... 62 Register Map Descriptions ............................................................. 67 Applications Information ............................................................... 82 Frequency Planning Using the AD9520 .................................. 82 Using the AD9520 Outputs for ADC Clock Applications .... 82 LVPECL Clock Distribution ...................................................... 82 CMOS Clock Distribution ......................................................... 83 Outline Dimensions ........................................................................ 84 Ordering Guide ........................................................................... 84 Rev Page AD9520-2 ...

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... AD9520-2 SPECIFICATIONS Typical (typ) is given for VS = VS_DRV = 3.3 V ± 5%; VS ≤ VCP ≤ 5. noted. Minimum (min) and maximum (max) values are given over full VS and T POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ VS 3.135 3.3 VS_DRV 2.375 VCP VS RSET Pin Resistor 4.12 CPRSET Pin Resistor 5 ...

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... P) Register 0x019[2:0]; see Table 53 Off 410 ps 530 ps 650 ps 770 ps 890 ps 1010 ps 1130 ps Register 0x019[5:3]; see Table 53 Off 370 ps 490 ps 610 ps 730 ps 850 ps 970 ps 1090 ps Rev Page AD9520-2 is possible possible < VCP − 0 the voltage on the CP (charge CP CP < VCP − 0 ...

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... AD9520-2 Parameter PHASE OFFSET IN ZERO DELAY Phase Offset (REF-to-LVPECL Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-LVPECL Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode ...

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... Using direct to output; see Figure 21 (higher frequencies are possible, but amplitude will not meet the V specification); the OD maximum output frequency is limited by either the maximum VCO frequency or the frequency at the CLK inputs, depending on the AD9520 configuration Single-ended; termination = 10 pF MHz See Figure load, VS_DRV = 3 ...

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... AD9520-2 TIMING CHARACTERISTICS Table 5. Parameter LVPECL OUTPUT RISE/FALL TIMES Output Rise Time Output Fall Time PROPAGATION DELAY CLK-TO-LVPECL OUTPUT PECL For All Divide Values Variation with Temperature 1 OUTPUT SKEW, LVPECL OUTPUTS LVPECL Outputs That Share the Same Divider LVPECL Outputs on Different Dividers ...

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... Timing Diagrams t CLK CLK t PECL t CMOS Figure 2. CLK/ CLK to Clock Output Timing, Div = 1 DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential t FP Rev Page SINGLE-ENDED 80% CMOS 10pF LOAD 20 Figure 4. CMOS Timing, Single-Ended Load AD9520-2 ...

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... AD9520-2 CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter CLK-TO-LVPECL ADDITIVE PHASE NOISE CLK = 1 GHz, Output = 1 GHz Divider = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 100 MHz Offset CLK = 1 GHz, Output = 200 MHz ...

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... Typ Max Unit 569 fs rms 599 fs rms Rev Page AD9520-2 Test Conditions/Comments Application example based on a typical setup where the reference source is clean wider PLL loop bandwidth is used; reference = 15.36 MHz; R DIV = 1 Integration BW = 200 kHz to 10 MHz Integration kHz to 20 MHz ...

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... AD9520-2 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 10. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER LVPECL = 245.76 MHz; PLL LBW = 125 Hz LVPECL = 122.88 MHz; PLL LBW = 125 Hz LVPECL = 61.44 MHz; PLL LBW = 125 Hz CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED) Table 11 ...

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... CS has an internal 30 kΩ pull-up resistor 2 μA −110 μA The minus sign indicates that current is flowing out of the AD9520, which is due to the internal pull-up resistor 2 pF SCLK has an internal 30 kΩ pull-down resistor in SPI mode, but not in I 2.0 V 0.8 V 110 μ ...

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... AD9520-2 SERIAL CONTROL PORT—I²C MODE Table 14. Parameter SDA, SCL (WHEN INPUTTING DATA) Input Logic 1 Voltage Input Logic 0 Voltage Input Current with an Input Voltage Between 0.1 × VS and 0.9 × VS Hysteresis of Schmitt Trigger Inputs Pulse Width of Spikes That Must Be Suppressed by the ...

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... Test Conditions/Comments Each of these pins has a 30 kΩ internal pull-up resistor 2 μA −110 μA The minus sign indicates that current is flowing out of the AD9520, which is due to the internal pull-up resistor 100 ns 1.3 ns High speed clock is CLK input signal Unit ...

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... AD9520-2 POWER DISSIPATION Table 18. Parameter POWER DISSIPATION, CHIP Power-On Default PLL Locked; One LVPECL Output Enabled PLL Locked; One CMOS Output Enabled Distribution Only Mode; VCO Divider On; One LVPECL Output Enabled Distribution Only Mode; VCO Divider Off; One LVPECL Output Enabled ...

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... JESD51-2. See the Thermal Performance section for more −0 0.3 V details. −0 0.3 V Table 20. Package Type 64-Lead LFCSP (CP-64-4) ESD CAUTION −0 0.3 V −0 0.3 V −0 0.3 V 150°C −65°C to +150°C 300°C Rev Page AD9520-2 θ Unit JA 22 °C/W ...

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... I Differential CLK clock input 14 I Differential CLK clock input VS 1 PIN 1 INDICATOR VCP AD9520 8 TOP VIEW LF 9 (Not to Scale CLK 13 CLK Figure 5. Pin Configuration Description 3.3 V Power Pins. Reference Monitor (Output). This pin has multiple selectable outputs. Lock Detect (Output). This pin has multiple selectable outputs. ...

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... Three-level logic. This pin is internally biased for the open logic level. Setting this pin high selects the register values stored in the internal EEPROM to be loaded at reset and/or power-up. Setting this pin low causes the AD9520 to load the hard-coded default register values at power-up/reset. This pin has an internal 30 kΩ ...

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... AD9520-2 Input/ Pin Pin No. Output Type Mnemonic 48 O LVPECL or OUT3 (OUT3A) CMOS 50 O LVPECL or OUT2 (OUT2B) CMOS 51 O LVPECL or OUT2 (OUT2A) CMOS 52 O LVPECL or OUT1 (OUT1B) CMOS 53 O OUT1 (OUT1A) LVPECL or CMOS 55 O LVPECL or OUT0 (OUT0B) CMOS 56 O LVPECL or OUT0 (OUT0A) ...

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... VOLTAGE ON CP PIN (V) Figure 9. Charge Pump Characteristics @ VCP = 3 PUMP DOWN 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOLTAGE ON CP PIN (V) Figure 10. Charge Pump Characteristics @ VCP = 5.0 V –140 –145 –150 –155 –160 –165 –170 0 PFD FREQUENCY (MHz) AD9520-2 3 PUMP UP 4.0 4 100 ...

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... AD9520-2 –208 –210 –212 –214 –216 –218 DIFFERENTIAL INPUT –220 –222 SINGLE-ENDED INPUT –224 0 0.2 0.4 0.6 0.8 INPUT SLEW RATE (V/ns) Figure 12. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/ REFIN 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 2.0 2.1 2 ...

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... Figure 23. Internal VCO Phase Noise (Absolute), Direct-to-LVPECL @ 2050 MHz Rev Page AD9520-2 0.5 1.0 1.5 2.0 2.5 FREQUENCY (GHz) 2pF 10pF 20pF 100 200 300 400 500 600 FREQUENCY (MHz) ...

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... AD9520-2 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 1k 10k 100k 1M FREQUENCY (Hz) Figure 24. Internal VCO Phase Noise (Absolute), Direct-to-LVPECL @ 2175 MHz –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 1k 10k 100k 1M FREQUENCY (Hz) Figure 25. Internal VCO Phase Noise (Absolute), Direct-to-LVPECL @ 2335 MHz – ...

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... Rev Page 10k 100k 1M 10M FREQUENCY (Hz) R2 390Ω 240nF C2 C3 62pF R1 33pF 820Ω BYPASS BYPASS C12 CAPACITOR 220nF FOR LDO R2 3kΩ 4.7µ 1.5nF 2.2nF R1 2.1kΩ BYPASS BYPASS C12 CAPACITOR 220nF FOR LDO AD9520-2 100M ...

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... AD9520-2 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter ...

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... STATUS PROGRAMMABLE A/B N DELAY PRESCALER COUNTERS N DIVIDER ZERO DELAY BLOCK DIVIDE DIVIDE DIVIDE DIVIDE DIVIDE Figure 36. Rev Page AD9520-2 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS VS_DRV OUT0 OUT0 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 ...

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... AD9520-2 THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9520 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 49 to Table 60). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. When the desired ...

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... A/B PROGRAMMABLE COUNTERS N DELAY N DIVIDER ZERO DELAY BLOCK DIVIDE DIVIDE DIVIDE DIVIDE DIVIDE Figure 37. Internal VCO and Clock Distribution (Mode 0) Rev Page AD9520-2 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS VS_DRV OUT0 OUT0 OUT1 OUT1 OUT2 OUT2 ...

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... AD9520-2 Mode 1: Clock Distribution or External VCO < 1600 MHz When the external clock source to be distributed or the external VCO/VCXO is <1600 MHz, a configuration that bypasses the VCO divider can be used. This is the only difference from Mode 2. Bypassing the VCO divider limits the frequency of the clock source to < ...

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... PROGRAMMABLE COUNTERS N DELAY N DIVIDER ZERO DELAY BLOCK DIVIDE DIVIDE DIVIDE DIVIDE DIVIDE Figure 38. Clock Distribution or External VCO < 1600 MHz (Mode 1) Rev Page AD9520-2 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS VS_DRV OUT0 OUT0 OUT1 OUT1 OUT2 OUT2 ...

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... AD9520-2 Mode 2: High Frequency Clock Distribution—CLK or External VCO > 1600 MHz The AD9520 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK input is connected to the distribution section through the VCO divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/ divide-by-5/divide-by-6) ...

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... DISTRIBUTION REFERENCE STATUS A/B PROGRAMMABLE COUNTERS N DELAY N DIVIDER ZERO DELAY BLOCK DIVIDE DIVIDE DIVIDE DIVIDE DIVIDE Rev Page AD9520-2 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS VS_DRV OUT0 OUT0 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 ...

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... In addition, the PLL can be used to clean up jitter and phase noise on a noisy reference. The exact choice of PLL parameters and loop dynamics is application specific. The flexibility and depth of the AD9520 PLL allow the part to be tailored to function in many different applications and signal environments. ...

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... PUMP Figure 41. Example of External Loop Filter for PLL PLL Reference Inputs The AD9520 features a flexible PLL reference input circuit that allows a fully differential input, two separate single-ended inputs 16.67 MHz to 33.33 MHz crystal oscillator with an on-chip maintaining amplifier. An optional reference clock doubler can be used to double the PLL reference frequency ...

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... PLL reference clock switching between REF1 (on Pin REFIN) and REF2 (on Pin REFIN ). This feature supports networking and other applications that require redundant references. The AD9520 features a dc offset option in single-ended mode. This option is designed to eliminate the risk of the reference inputs chattering when they are ac-coupled and the reference clock disappears ...

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... VCO frequency is greater than 2400 MHz because the frequency going to the A/B counter is too high. When the AD9520 B counter is bypassed (B = 1), the A counter should be set to zero, and the overall resulting divide is equal to the prescalar setting, P. The possible divide ratios in this mode are 16, and 32 ...

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... Note that it is possible in certain low (<500 Hz) loop bandwidth, high phase margin cases that the DLD can chatter during acqui- sition, which can cause the AD9520 to automatically enter and exit holdover. To avoid this problem recommended that the user make provisions for a capacitor to ground on the LD pin so that current source digital lock detect (CSDLD) mode can be used ...

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... External VCXO/VCO Clock Input (CLK/ CLK ) This differential input is used to drive the AD9520 clock distribution section. This input can receive up to 2.4 GHz. The pins are internally self-biased, and the input signal should be ac-coupled via capacitors. CLOCK INPUT STAGE VS CLK CLK 2.5kΩ ...

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... AD9520-2 PLL ENABLED DLD == LOW YES WAS LD PIN == HIGH WHEN DLD WENT LOW? YES HIGH IMPEDANCE CHARGE PUMP YES REFERENCE EDGE AT PFD? YES RELEASE CHARGE PUMP HIGH IMPEDANCE YES DLD == HIGH The holdover function senses the logic level of the LD pin as a condition to enter holdover. The signal at LD can be from the DLD, ALD, or current source LD mode (CSDLD) ...

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... Frequency Status Monitors The AD9520 contains three frequency status monitors that are used to indicate if the PLL reference (or references in the case of single-ended mode) and the VCO have fallen below a threshold frequency. A diagram showing their location in the PLL is shown in Figure 47 ...

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... PLL locks. A SYNC is executed during the VCO calibration; therefore, the outputs of the AD9520 are held static during the calibration, which prevents unwanted frequencies from being produced. However, at the end of a VCO calibration, the outputs may resume clocking before the PLL loop is completely settled. ...

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... PLL reference input. There are two zero delay modes on the AD9522: internal and external. Internal Zero Delay Mode The internal zero delay function of the AD9520 is achieved by feeding the output of Channel Divider 0 back to the PLL N divider. In Figure 48, the change in signal routing for internal zero delay mode is shown in blue ...

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... The VCO divider has two purposes. The first is to limit the maximum input frequency of the channel dividers to 1.6 GHz. The other is to allow the AD9520 to generate even lower frequencies than would be possible with only a simple post divider. External clock signals connected to the CLK input can also use the VCO divider ...

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... The high and low cycles are cycles of the clock signal currently routed to the input of the channel dividers (VCO divider out or CLK). When a divider is bypassed, D Otherwise This allows X each channel divider to divide by any integer from 1 to 32. Rev Page AD9520-2 for the Output Dividers X High Cycles Disable N Bypass Div DCC 0x190[3:0] ...

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... AD9520-2 Duty Cycle and Duty-Cycle Correction The duty cycle of the clock signal at the output of a channel is a result of some or all of the following conditions: • The M and N values for the channel • DCC enabled/disabled • VCO divider enabled/bypassed • The CLK input duty cycle (note that the internal VCO has a 50% duty cycle) The DCC function is enabled by default for each channel divider ...

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... The timing of the SYNC operation is shown in VCO divider) and in There is an uncertainty one cycle of the clock at the input to the channel divider due to the asynchronous nature of the SYNC signal with respect to the clock edges inside the AD9520. Rev Page AD9520 ...

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... SYNC operation. Between outputs and after synchronization, this allows for the setting of phase offsets. The AD9520 differential LVPECL outputs are four groups of three, sharing a channel divider per triplet. In the case of CMOS, each LVPECL differential pair can be configured as two single- ended CMOS outputs ...

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... CMOS output register (0x0F0[6:5] to 0x0FB[6:5]). The CMOS driver is in tristate when it is powered down. RESET MODES The AD9520 has a power-on reset (POR) and several other ways to apply a reset condition to the chip. Power-On Reset During chip power-up, a power-on reset pulse is issued when VS reaches ~2.6 V (< ...

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... Because this is not a complete power-down, it can be called sleep mode. The AD9520 contains special circuitry to prevent runt pulses on the outputs when the chip is entering or exiting sleep mode. When the AD9520 power-down, the chip is in the following state: • The PLL is off (asynchronous power-down). ...

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... The AD9520 I2C port has a 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL I2C bus system, the AD9520 is connected to the serial bus (data bus SDA and clock bus SCL slave device, meaning that no clock is generated by the AD9520. The AD9520 uses direct 16-bit (two bytes) memory addressing instead of traditional 8-bit (one byte) memory addressing ...

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... AD9520-2 SDA MSB SCL SDA MSB = 0 SCL Figure 58. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration) MSB = 1 SDA SCL Figure 59. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration) The no acknowledge bit is the ninth bit attached to any 8-bit data byte ...

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... SET; STR HIGH Sr Figure 60. I²C Serial Port Timing Rev Page RAM Address Low Byte A RAM Data 1 A RAM Data 2 A RAM Data 2 RAM RAM R A Data 0 A Data RISE SPIKE t t IDLE HLD; STR t SET; STP P AD9520 RAM A Data ...

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... SDO). By default, the AD9520 is in bidirectional mode. Short instruction mode (8-bit instructions) is not supported. Only long (16-bit) instruction mode is supported. A write or a read operation to the AD9520 is initiated by pulling CS low. The CS stalled high mode is supported in data transfers where three or fewer bytes of data (plus instruction data) are transferred ...

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... In MSB first mode, subsequent bytes increment the address. SPI MSB/LSB FIRST TRANSFERS The AD9520 instruction word and byte data can be MSB first or LSB first. Any data written to 0x000 must be mirrored; the upper four bits ([7:4]) must mirror the lower four bits ([3:0]). ...

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... AD9520-2 Table 45. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 R A12 = 0 CS SCLK DON'T CARE SDIO R A12 A11 A10 DON'T CARE 16-BIT INSTRUCTION HEADER Figure 63. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data ...

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... Minimum period that SCLK should logic high state HIGH t Minimum period that SCLK should logic low state LOW t SCLK to valid SDIO and SDO (see Figure 66 CLK t t HIGH LOW t DH BIT N BIT Figure 68. Serial Control Port Timing—Write Rev Page AD9520 ...

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... SPI mode, users can read the value of STATUS_EEPROM ( process and 0 = completed). In I2C mode, the user can address the AD9520 slave port with the external I2C master (send an address byte to the AD9520). If the AD9520 responds with a no acknowledge bit, the data transfer process is not done ...

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... EEPROM, the register values loaded from the EEPROM are not transferred to the active register space, and these values do not take effect after they are loaded from the EEPROM to the AD9520. End-of-Data (Operational Code 0xFF) The EEPROM controller uses this operational code to terminate the data transfer process between EEPROM and the control register during the upload and download process ...

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... AD9520-2 Table 47. Example of an EEPROM Buffer Segment Reg Addr (Hex) Bit 7 (MSB) Start EEPROM Buffer Segment 0xA00 0 0xA01 0xA02 0xA03 0 0xA04 0xA05 0xA06 0 0xA07 0xA08 0xA09 0xA0A Bit 6 Bit 5 Bit 4 Bit 3 Number of bytes [6:0] of the first group of registers Address [15:8] of the first group of registers ...

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... Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1 JC Ψ Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air) JT The AD9520 is specified for a case temperature (T that T is not exceeded, an airflow source can be used. CASE Use the following equation to determine the junction ...

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... AD9520-2 REGISTER MAP Register addresses that are not listed in Table 49 are not used, and writing to those registers has no effect. Writing to register addresses marked unused also has no effect. Table 49. Register Map Overview Addr (Hex) Parameter Bit 7 (MSB) Serial Port Configuration 000 Serial port config ...

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... Unused CSDLD En OUT11 Unused Divider 0 low cycles Divider 0 Divider 0 Divider 0 ignore force start high SYNC high Unused Unused Rev Page AD9520-2 Bit 2 Bit 1 Bit 0 (LSB) Enable Enable Unused external zero delay zero delay REF2 REF1 freq > Digital lock freq > threshold detect ...

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... AD9520-2 Addr (Hex) Parameter Bit 7 (MSB) 193 Divider 1 (PECL) 194 Divider 1 bypass 195 196 Divider 2 (PECL) 197 Divider 2 bypass 198 199 Divider 3 (PECL) 19A Divider 3 bypass 19B 19C to 1DF VCO Divider and CLK Input 1E0 VCO divider 1E1 Input CLKs Unused ...

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... EEPROM Buffer Segment Register 16 (default: number of bytes for Group 6) EEPROM Buffer Segment Register 19 (default: number of bytes for Group 7) EEPROM Buffer Segment Register 22 (default: IO_UPDATE from EEPROM) EEPROM Buffer Segment Register 23 (default: end of data) Unused Rev Page AD9520-2 Bit 2 Bit 1 Bit 0 (LSB) Default Value ...

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... AD9520-2 Addr (Hex) Parameter Bit 7 (MSB) EEPROM Control B00 EEPROM status (read-only) B01 EEPROM error checking (read-only) B02 EEPROM Control 1 B03 EEPROM Control 2 Bit 6 Bit 5 Bit 4 Bit 3 Unused Unused Unused Unused Rev Page Bit 2 Bit 1 Bit 0 (LSB) Unused STATUS_ EEPROM Unused ...

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... Description 16-bit EEPROM ID[7:0]. This register, along with 0x006, allows the user to store a unique ID to identify which version of the AD9520 register settings is stored in the EEPROM. It does not affect AD9520 operation in any way (default: 0x00). 16-bit EEPROM ID[15:8]. This register, along with 0x005, allows the user to store a unique ID to identify which version of the AD9520 register settings is stored in the EEPROM ...

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... AD9520-2 Table 53. PLL Reg. Addr (Hex) Bit(s) Name Description 010 [7] PFD polarity Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires positive polarity [ [ positive (higher control voltage produces higher frequency) (default). [ negative (higher control voltage produces lower frequency). ...

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... Holdover active (active high LVL LD pin comparator output (active high LVL VS (PLL power supply DYN REF1 clock (differential reference when in differential mode DYN REF2 clock (not available in differential mode DYN Selected reference to PLL (differential reference when in differential mode). Rev Page AD9520-2 ...

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... AD9520-2 Reg. Addr (Hex) Bit(s) Name Description [7] [6] [ 017 [1:0] Antibacklash [1] [0] Antibacklash Pulse Width (ns) pulse width 018 [7] Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost. Enable CMOS reference input [ disable dc offset (default). dc offset [ enable dc offset. ...

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... LVL Status of VCO frequency (active high LVL Selected reference (low = REF1, high = REF2 LVL DLD; active high LVL Holdover active (active high LVL N/A, do not use LVL VS (PLL supply DYN REF1 clock (differential reference when in differential mode). Rev Page AD9520-2 ...

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... AD9520-2 Reg. Addr (Hex) Bit(s) Name Description [5] [4] [ 01B [7] Enable VCO Enables or disables VCO frequency monitor. frequency [ disable the VCO frequency monitor (default). monitor [ enable the VCO frequency monitor. 01B [6] Enable REF2 Enables or disables the REF2 frequency monitor. (REFIN) [ disable the REF2 frequency monitor (default). ...

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... LVL (DLD) AND (status of selected reference) AND (status of VCO LVL Status of VCO frequency (active low LVL Selected reference (low = REF2, high = REF1 LVL DLD; active low LVL Holdover active (active low LVL LD pin comparator output (active low). Rev Page AD9520-2 ...

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... Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode. comparator When the AD9520 is in internal (automatic) holdover mode, this enables the use of the voltage on the LD pin to determine if the PLL was previously in a locked state (see Figure 46). Otherwise, this can be used with the REFMON and STATUS pins to monitor the voltage on the LD pin. [ ...

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... On On [4] [3] Output Type X 0 (default) LVPECL X 1 LVPECL 0 (default) 0 CMOS 0 1 CMOS 1 0 CMOS 1 1 CMOS ). OD [1] V (mV 400 1 600 0 (default) 780 1 960 Rev Page AD9520-2 OUT0A OUT0B Noninverting Inverting Inverting Noninverting Noninverting Noninverting Inverting Inverting Noninverting Inverting Inverting Noninverting ...

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... AD9520-2 Reg. Addr (Hex) Bit(s) Name Description 0F6 [7:0] OUT6 control This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0. 0F7 [7:0] OUT7 control This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0. ...

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... Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x1 means the divider is high for two input clock cycles (default: 0x1). Bypasses and powers down the divider; routes input to divider output. [ use divider (default). [ bypass divider. Rev Page AD9520-2 ...

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... AD9520-2 Reg. Addr (Hex) Bit(s) Name 197 [6] Divider 2 ignore SYNC 197 [5] Divider 2 force high 197 [4] Divider 2 start high 197 [3:0] Divider 2 phase offset 198 [2] Channel 2 power-down 198 [1] Channel 2 direct-to-output 198 [0] Disable Divider 2 DCC 199 [7:4] Divider 3 low cycles 199 [3:0] Divider 3 high cycles ...

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... VCO as input to VCO divider; cannot bypass VCO divider when this is selected. This bit must be set to use the PLL with the internal VCO. Bypasses or uses the VCO divider. [ use VCO divider (default). [ bypass VCO divider; cannot select VCO as input when this is selected. Rev Page AD9520-2 Divide 2 (default ...

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... EEPROM. Because the AD9520 register space is noncontiguous, to EEPROM Buffer the EEPROM controller needs to know the starting address and number of bytes in the AD9520 register Segment Register 23 space to store and retrieve from the EEPROM. In addition, there are special instructions for the EEPROM controller, operational codes (that is, IO_UPDATE and end-of-data) that are also stored in the EEPROM buffer segment ...

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... Data is correct. (read-only) [ incorrect data detected. B02 [1] Soft_EEPROM When the EEPROM pin is tied low, setting Soft_EEPROM resets the AD9520 using the settings saved in EEPROM. [ soft reset with EEPROM settings (self-clearing). B02 [0] Enable EEPROM Enables the user to write to the EEPROM. ...

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... USING THE AD9520 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed ADC is extremely sensitive to the quality of the sampling clock of the AD9520. An ADC can be thought sampling mixer, and any noise, distortion, or time jitter on the clock is combined with the desired signal at the analog-to- digital output ...

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... Termination at the far end of the PCB trace is a second option VS_DRV S The CMOS outputs of the AD9520 do not supply enough current 50Ω to provide a full voltage swing with a low impedance resistive, far- LVPECL end termination, as shown in Figure 74. The far-end termination 50Ω ...

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... SEATING PLANE ORDERING GUIDE Model Temperature Range AD9520-2BCPZ 1 −40°C to +85°C 1 AD9520-2BCPZ-REEL7 −40°C to +85°C 1 AD9520-2/PCBZ RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 9.00 BSC SQ ...