AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 12

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9520-3
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CMOS OUTPUT ADDITIVE TIME JITTER
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
CLK = 622.08 MHz
CLK = 622.08 MHz
CLK = 1000 MHz
CLK = 500 MHz
CLK = 200 MHz
Any LVPECL Output = 622.08 MHz
Divide Ratio = 1
Any LVPECL Output = 155.52 MHz
Divide Ratio = 4
Any LVPECL Output = 100 MHz
Divide Ratio = 10
Any LVPECL Output = 100 MHz
Divide Ratio = 5
Any CMOS Output Pair = 100 MHz
Divide Ratio = 2
Min
Min
Typ
54
77
109
79
114
163
124
176
259
Rev. 0 | Page 12 of 84
Typ
46
64
223
209
325
Max
Max
Unit
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Unit
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Test Conditions/Comments
Application example based on a typical setup using an
external 245.76 MHz VCXO (Toyocom TCO-2112);
reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Distribution section only; does not include
PLL and VCO; measured at rising edge of
clock signal
BW = 12 kHz − 20 MHz
BW = 12 kHz − 20 MHz
Calculated from SNR of ADC method
Broadband jitter
Calculated from SNR of ADC method
Broadband jitter
Distribution section only; does not include
PLL and VCO
Calculated from SNR of ADC method
Broadband jitter