AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 46

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9520-3
Duty Cycle and Duty-Cycle Correction
The duty cycle of the clock signal at the output of a channel is a
result of some or all of the following conditions:
• The M and N values for the channel
• DCC enabled/disabled
• VCO divider enabled/bypassed
• The CLK input duty cycle (note that the internal VCO has a
The DCC function is enabled by default for each channel divider.
However, the DCC function can be disabled individually for
each channel divider by setting the disable divider DCC bit for
that channel.
Certain M and N values for a channel divider result in a non-
50% duty cycle. A non-50% duty cycle can also result with an
even division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle.
Duty-cycle correction requires the following channel divider
conditions:
• An even division must be set as M = N
• An odd division must be set as M = N + 1
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2) expressed as a percent.
The duty cycle at the output of the channel divider for various
configurations is shown in Table 35 to Table 38.
Table 35. Channel Divider Output Duty Cycle with VCO
Divider ≠ 1, Input Duty Cycle Is 50%
VCO
Divider
Even
Odd = 3
Odd = 5
Even, odd
Even, odd
50% duty cycle)
N + M + 2
Channel
divider
bypassed
Channel
divider
bypassed
Channel
divider
bypassed
Even
Odd
D
X
Disable Div
DCC = 1
50%
33.3%
40%
(N + 1)/(N + M + 2)
(N + 1)/(N + M + 2)
Output Duty Cycle
Disable Div
DCC = 0
50%
50%
50%
50%, requires
M = N
50%, requires
M = N + 1
Rev. 0 | Page 46 of 84
Table 36. Channel Divider Output Duty Cycle with VCO
Divider ≠ 1, Input Duty Cycle Is X%
VCO
Divider
Even
Odd = 3
Odd = 5
Even
Even
Odd = 3
Odd = 3
Odd = 5
Odd = 5
Table 37. Channel Divider Output Duty Cycle When the
VCO Divider Is Enabled and Set to 1
Input
Clock
Duty Cycle
Any
50%
X%
Note that the channel divider must be enabled when VCO divider = 1.
Table 38. Channel Divider Output Duty Cycle When the
VCO Divider Is Bypassed
Input
Clock
Duty Cycle
Any
Any
50%
X%
N + M + 2
Channel
divider
bypassed
Channel
divider
bypassed
Channel
divider
bypassed
Even
Odd
Even
Odd
Even
Odd
N + M + 2
Even
Odd
Odd
N + M + 2
Channel
divider
bypassed
Even
Odd
Odd
D
X
D
D
X
X
Disable Div
DCC = 1
50%
33.3%
40%
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
Disable Div
DCC = 1
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
Disable Div
DCC = 1
Same as input
duty cycle
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
Output Duty Cycle
Output Duty Cycle
Output Duty Cycle
Disable Div DCC = 0
50%
(1 + X%)/3
(2 + X%)/5
50%, requires M = N
50%, requires M = N + 1
50%, requires M = N
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
50%, requires M = N
(5N + 7 + X%)/(10N + 15),
requires M = N + 1
Disable Div DCC = 0
50%, requires M = N
50%, requires M = N + 1
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
Disable Div DCC = 0
Same as input duty
cycle
50%, requires M = N
50%, requires M = N + 1
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1