AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 47

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Divider
0
1
2
3
The internal VCO has a duty cycle of 50%. Therefore, when the
VCO is connected directly to the output, the duty cycle is 50%.
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
Phase Offset or Coarse Time Delay
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 39).
These settings determine the number of cycles (successive rising
edges) of the channel divider input frequency by which to offset, or
delay, the rising edge of the output of the divider. This delay is
with respect to a nondelayed output (that is, with a phase offset
of zero). The amount of the delay is set by five bits loaded into
the phase offset (PO) register plus the start high (SH) bit for
each channel divider. When the start high bit is set, the delay is
also affected by the number of low cycles (M) programmed for
the divider.
It is necessary to use the SYNC function to make phase offsets
effective (see the Synchronizing the Outputs—SYNC Function
section).
Table 39. Setting Phase Offset and Division
Let
Δ
Δ
T
seconds).
Φ =
16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The channel divide by is set as N = high cycles and M = low
cycles.
Case 1
For Φ ≤ 15,
Δ
Δ
Case 2
For Φ ≥ 16,
Δ
Δ
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 50 shows the results of setting such a coarse
offset between outputs.
X
t
c
t
c
t
c
= delay (in seconds).
= Φ × T
= (Φ − 16 + M + 1) × T
= delay (in cycles of clock signal at input to D
= Δ
= Δ
= period of the clock signal at the input of the divider, D
t
t
/T
/T
X
X
Start
High (SH)
0x191[4]
0x194[4]
0x197[4]
0x19A[4]
X
= Φ
Phase
Offset (PO)
0x191[3:0]
0x194[3:0]
0x197[3:0]
0x19A[3:0]
X
Low Cycles
M
0x190[7:4]
0x193[7:4]
0x196[7:4]
0x199[7:4]
X
).
High Cycles
N
0x190[3:0]
0x193[3:0]
0x196[3:0]
0x199[3:0]
X
Rev. 0 | Page 47 of 84
(in
DIVIDER 0
DIVIDER 1
DIVIDER 2
Synchronizing the Outputs—SYNC Function
The AD9520 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions. These conditions include the
divider ratio and phase offsets for a given channel divider. This
allows the user to specify different divide ratios and phase offsets
for each of the four channel dividers. Releasing the SYNC pin
allows the outputs to continue clocking with the preset conditions
applied.
Synchronization of the outputs is executed in several ways:
• The SYNC pin is forced low and then released (manual sync).
• By setting and then resetting any one of the following three
• Synchronization of the outputs can be executed as part of the
• The RESET pin is forced low and then released (chip reset).
• The PD pin is forced low and then released (chip power-down).
• Whenever a VCO calibration is completed, an internal SYNC
The most common way to execute the SYNC function is to use
the SYNC pin to perform a manual synchronization of the outputs.
This requires a low-going signal on the SYNC pin, which is held
low and then released when synchronization is desired. The
timing of the SYNC operation is shown in
VCO divider) and in
There is an uncertainty of up to 1 cycle of the clock at the input
to the channel divider due to the asynchronous nature of the
SYNC signal with respect to the clock edges inside the AD9520.
DIVIDER INPUT
bits: the soft SYNC bit (0x230[0]), the soft reset bit (0x000[5]
[mirrored]), and the power-down distribution reference bit
(0x230[1]).
chip power-up sequence.
signal is automatically asserted at the beginning and released
upon the completion of a VCO calibration.
CHANNEL
PO = 0
PO = 1
PO = 2
SH = 0
SH = 0
SH = 0
Figure 50. Effect of Coarse Phase Offset (or Delay)
0
1
Tx
2
Figure 52
3
1 × Tx
2 × Tx
4
CHANNEL DIVIDER OUTPUTS
5
(the VCO divider not used).
DIV = 4, DUTY = 50%
6
7
8
9 10 11 12 13 14 15
Figure 51
AD9520-3
(using the