AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 52

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9520-3
The no acknowledge bit is the ninth bit attached to any 8-bit
data byte. A no acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has not been received. It is done by leaving the SDA line
high during the ninth clock pulse after each 8-bit data byte.
Data Transfer Process
The master initiates data transfer by asserting a start condition.
This indicates that a data stream follows. All I2C slave devices
connected to the serial bus respond to the start condition.
The master then sends an 8-bit address byte over the SDA line,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device
(0 = write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by sending an acknowledge bit. All other
devices on the bus remain idle while the selected device waits
for data to be read from or written to it. If the R/W bit is 0, the
master (transmitter) writes to the slave device (receiver). If the
R/W bit is 1, the master (receiver) reads from the slave device
(transmitter).
The format for these commands is described in the Data
Transfer Format section.
SDA
SDA
SDA
SCL
SCL
SCL
S
S
S
MSB = 0
MSB = 1
MSB
1
1
1
Figure 58. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration)
Figure 59. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration)
2
2
2
3 TO 7
3 TO 7
3 TO 7
8
8
8
ACKNOWLEDGE FROM
ACKNOWLEDGE FROM
ACKNOWLEDGE FROM
Figure 57. Acknowledge Bit
MASTER-RECEIVER
SLAVE-RECEIVER
SLAVE-RECEIVER
Rev. 0 | Page 52 of 84
9
9
9
Data is then sent over the serial bus in the format of nine clock
pulses, one data byte (8-bit) from either master (write mode) or
from slave (read mode) followed by an acknowledge bit from
the receiving device. The number of bytes that can be transmitted
per transfer is unrestricted. In write mode, the first two data
bytes immediately after the slave address byte are the internal
memory (control registers) address bytes with the high address
byte first. This addressing scheme gives a memory address up to
2
bytes are register data written into the control registers. In read
mode, the data bytes after the slave address byte are register
data read from the control registers.
When all data bytes are read or written, stop conditions are
established. In write mode, the master (transmitter) asserts a
stop condition to end data transfer during the (10th) clock
pulse following the acknowledge bit for the last data byte from
the slave device (receiver). In read mode, the master device
(receiver) receives the last data byte from the slave device
(transmitter) but does not pull it low during the ninth clock
pulse. This is known as a no acknowledge bit. By receiving the no
acknowledge bit, the slave device knows that the data transfer is
finished and releases the SDA line. The master then takes the
data line low during the low period before the 10th clock pulse,
and high during the 10th clock pulse to assert a stop condition.
A repeated start (Sr) condition can be used in place of a stop
condition. Furthermore, a start or stop condition can occur at
any time and partially transferred bytes are discarded.
1
1
1
16
− 1 = 65,535. The data bytes after these two memory address
2
2
2
3 TO 7
3 TO 7
3 TO 7
ACKNOWLEDGE FROM
ACKNOWLEDGE FROM
8
8
8
SLAVE-RECEIVER
NO ACKNOWLEDGE
SLAVE-RECEIVER
SLAVE-RECEIVER
FROM
9
9
9
10
10
10
P
P
P