AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 6

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9520-3
Parameter
PHASE OFFSET IN ZERO DELAY
NOISE CHARACTERISTICS
PLL DIGITAL LOCK DETECT WINDOW
1
2
The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
In-Band Phase Noise of the Charge Pump/
PLL Figure of Merit (FOM)
Lock Threshold (Coincidence of Edges)
Unlock Threshold (Hysteresis)
Phase Offset (REF-to-LVPECL Clock Output
Phase Offset (REF-to-LVPECL Clock Output
Phase Offset (REF-to-CLK Input Pins) in
Phase Offset (REF-to-CLK Input Pins) in
Pins) in Internal Zero Delay Mode
Pins) in Internal Zero Delay Mode
External Zero Delay Mode
External Zero Delay Mode
Phase Frequency Detector (In-Band
Means Within the LBW of the PLL)
@ 500 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ 10 MHz PFD Frequency
@ 50 MHz PFD Frequency
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
2
2
Min
560
−320
140
−460
Typ
1060
+50
630
−20
−165
−162
−152
−144
−222
3.5
7.5
3.5
7
15
11
Rev. 0 | Page 6 of 84
Max
1310
+240
870
+200
Unit
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
REF refers to REFIN (REF1)/REFIN (REF2)
When N delay and R delay are bypassed
When N delay and R delay are bypassed
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output of
the VCO and subtracting 20 log(N) (where N is the value
of the N divider)
Reference slew rate > 0.5 V/ns; FOM + 10 log(f
approximation of the PFD/CP in-band phase noise (in
the flat region) inside the PLL loop bandwidth; when
running closed-loop, the phase noise, as observed at
the VCO output, is increased by 20 log(N); PLL figure of
merit decreases with decreasing slew rate; see Figure 12
Signal available at LD, STATUS, and REFMON pins when
selected by appropriate register settings; lock detect
window settings can be varied by changing the
CPRSET resistor
Selected by 0x017[1:0] and 0x018[4]
(this is the threshold to go from unlock to lock)
0x017[1:0] = 00b, 01b,11b; 0x018[4] = 1b
This is the threshold to go from lock to unlock
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b
0x017[1:0] = 10b; 0x018[4] = 0b
When N delay = Setting 110 and R delay is bypassed
When N delay = Setting 011 and R delay is bypassed
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b
0x017[1:0] = 10b; 0x018[4] = 0b
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b
PFD
) is an