AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 63

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Addr
(Hex)
01E
01F
Output Driver Control
0F0
0F1
0F2
0F3
0F4
0F5
0F6
0F7
0F8
0F9
0FA
0FB
0FC
0FD
0FE
to
18F
LVPECL Channel Dividers
190
191
192
Parameter
PLL_CTRL_9
PLL_Readback
(read-only)
OUT0 control
OUT1 control
OUT2 control
OUT3 control
OUT4 control
OUT5 control
OUT6 control
OUT7 control
OUT8 control
OUT9 control
OUT10 control
OUT11 control
Enable output
on CSDLD
Enable output
on CSDLD
Divider 0 (PECL)
Bit 7 (MSB)
Unused
OUT0 format
OUT1 format
OUT2 format
OUT3 format
OUT4 format
OUT5 format
OUT6 format
OUT7 format
OUT8 format
OUT9 format
OUT10 format
OUT11 format
CSDLD En
Out 7
Unused
Divider 0
bypass
Unused
Divider 0 low cycles
Bit 6
VCO cal
finished
CSDLD En
OUT6
Unused
Divider 0
ignore
SYNC
OUT10 CMOS
OUT11 CMOS
configuration
configuration
configuration
configuration
configuration
configuration
configuration
configuration
configuration
configuration
configuration
configuration
Unused
OUT0 CMOS
OUT1 CMOS
OUT2 CMOS
OUT3 CMOS
OUT4 CMOS
OUT5 CMOS
OUT6 CMOS
OUT7 CMOS
OUT8 CMOS
OUT9 CMOS
Bit 5
Holdover
active
CSDLD En
OUT5
Unused
Divider 0
force
high
Rev. 0 | Page 63 of 84
Bit 4
REF2
selected
CSDLD En
OUT4
Unused
Divider 0
start high
channel divider select
External zero delay
OUT10 polarity
OUT11 polarity
OUT0 polarity
OUT1 polarity
OUT2 polarity
OUT3 polarity
OUT4 polarity
OUT5 polarity
OUT6 polarity
OUT7 polarity
OUT8 polarity
OUT9 polarity
feedback
Unused
Bit 3
VCO freq >
threshold
CSDLD En
OUT3
CSDLD En
OUT11
Unused
Bit 2
Enable
external
zero delay
REF2 freq
>
threshold
CSDLD
En
OUT2
CSDLD
En
OUT10
Channel 0
power-
down
Divider 0 high cycles
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
OUT10 LVPECL
OUT11 LVPECL
OUT0 LVPECL
OUT1 LVPECL
OUT2 LVPECL
OUT3 LVPECL
OUT4 LVPECL
OUT5 LVPECL
OUT6 LVPECL
OUT7 LVPECL
OUT8 LVPECL
OUT9 LVPECL
phase offset
Divider 0
Bit 1
Enable
zero delay
REF1 freq >
threshold
CSDLD En
OUT1
CSDLD En
OUT9
Channel 0
direct-to-
output
Bit 0 (LSB)
Unused
Digital lock
detect
OUT0
LVPECL
power-down
OUT1
LVPECL
power-down
OUT2
LVPECL
power-down
OUT3
LVPECL
power-down
OUT4
LVPECL
power-down
OUT5
LVPECL
power-down
OUT6
LVPECL
power-down
OUT7
LVEPCL
power-down
OUT8
LVPECL
power-down
OUT9
LVPECL
power-down
OUT10
LVPECL
power-down
OUT11
LVPECL
power-down
CSDLD En
OUT0
CSDLD En
OUT8
Divider 0
Disable
DCC
AD9520-3
Default
Value
(Hex)
00
N/A
64
64
64
64
64
64
64
64
64
64
64
64
00
00
77
00
00
00