AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 68

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
010
010
010
010
011
012
013
014
015
016
016
016
016
AD9520-3
Table 53. PLL
[7]
[6:4] CP current
[3:2] CP mode
[1:0] PLL power-
[7:0] 14-bit R counter,
[5:0] 14-bit R counter,
[5:0] 6-bit A counter
[7:0] 13-bit B counter,
[4:0] 13-bit B counter,
[7]
[6]
[5]
[4]
PFD polarity
down
Bits[7:0] (LSB)
Bits[13:8] (MSB)
Bits[7:0] (LSB)
Bits[12:8] (MSB)
Set CP pin
to VCP/2
Reset R counter Reset R counter (R divider).
Reset A and B
counters
Reset all
counters
Description
Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only.
The on-chip VCO requires positive polarity [7] = 0.
[7] = 0; positive (higher control voltage produces higher frequency) (default).
[7] = 1; negative (higher control voltage produces lower frequency).
Charge pump current (with CPRSET = 5.1 kΩ).
[6]
0
0
0
0
1
1
1
1
Charge pump operating mode.
[3]
0
0
1
1
PLL operating mode.
[1]
0
0
1
1
Reference divider LSBs—lower eight bits. The reference divider (also called the R divider or R counter) is
14 bits long. The lower eight bits are in this register (default: 0x01).
Reference divider MSBs—upper six bits. The reference divider (also called the R divider or R counter) is
14 bits long. The upper six bits are in this register (default: 0x00).
A counter (part of N divider). The N divider is also called the feedback divider (default: 0x00).
B counter (part of N divider)—lower eight bits. The N divider is also called the feedback divider (default: 0x03).
B counter (part of N divider)—upper five bits. The N divider is also called the feedback divider (default: 0x00).
Sets the CP pin to one-half of the VCP supply voltage.
[7] = 0; CP normal operation (default).
[7] = 1; CP pin set to VCP/2.
[6] = 0; normal (default).
[6] = 1; hold R counter in reset.
Reset A and B counters (part of N divider).
[5] = 0; normal (default).
[5] = 1; hold A and B counters in reset.
Reset R, A, and B counters.
[4] = 0; normal (default).
[4] = 1; hold R, A, and B counters in reset.
[5]
0
0
1
1
0
0
1
1
[2]
0
1
0
1
[0]
0
1
0
1
[4]
1
Unused.
Synchronous power-down.
0
1
0
1
0
1
0
Charge Pump Mode
High impedance state.
Force source current (pump up).
Force sink current (pump down).
Normal operation (default).
Mode
Normal operation; this mode must be selected to use the PLL.
Asynchronous power-down (default).
I
0.6
1.2
1.8
2.4
3.0
3.6
4.2
4.8 (default)
CP
(mA)
Rev. 0 | Page 68 of 84