AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 73

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
01C
01C
01C
01C
01C
01C
01C
01C
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Disable
switchover
deglitch
Select REF2
Use REF_SEL
pin
Enable
automatic
reference
switchover
Stay on REF2
Enable REF2
Enable REF1
Enable
differential
reference
Description
[4]
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Disables or enables the switchover deglitch circuit.
[7] = 0; enable switchover deglitch circuit (default).
[7] = 1; disable switchover deglitch circuit.
If Register 0x01C[5] = 0, selects reference for PLL when in manual; register selected reference control.
[6] = 0; select REF1 (default).
[6] = 1; select REF2.
If Register 0x01C[4] = 0 (manual), sets method of PLL reference selection.
[5] = 0; use Register 0x01C[6] (default).
[5] = 1; use REF_SEL pin.
Automatic or manual reference switchover. Single-ended reference mode must be selected by
Register 0x01C[0] = 0.
[4] = 0; manual reference switchover (default).
[4] = 1; automatic reference switchover.
Setting this bit also powers on REF1 and REF2, and overrides the setting in Register 0x01C[2:1].
Stays on REF2 after switchover.
[3] = 0; return to REF1 automatically when REF1 status is good again (default).
[3] = 1; stay on REF2 after switchover. Do not automatically return to REF1.
This bit turns the REF2 power on. This bit is overridden when automatic reference switchover is enabled.
[2] = 0; REF2 power off (default).
[2] = 1; REF2 power on.
This bit turns the REF1 power on. This bit is overridden when automatic reference switchover is enabled.
[1] = 0; REF1 power off (default).
[1] = 1; REF1 power on.
Selects the PLL reference mode, differential or single-ended.
Register 0x01C[2:1] should be cleared when this bit is set.
[0] = 0; single-ended reference mode (default).
[0] = 1; differential reference mode.
[3]
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
[2]
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
[1]
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Level or
Dynamic
Signal
LVL
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
Rev. 0 | Page 73 of 84
Signal at REFMON Pin
Holdover active (active high).
N/A, do not use.
VS (PLL supply).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available when in differential mode).
Status of selected reference (status of differential reference);
active low.
Status of unselected reference (not available in differential mode);
active low.
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
(Status of REF1 frequency) AND (status of REF2 frequency) .
(DLD) AND (status of selected reference) AND (status of VCO) .
Status of VCO frequency (active low).
Selected reference (low = REF2, high = REF1).
DLD; active low.
Holdover active (active low).
N/A, do not use.
AD9520-3