AD9600ABCPZ-125 Analog Devices Inc, AD9600ABCPZ-125 Datasheet
AD9600ABCPZ-125
Specifications of AD9600ABCPZ-125
Related parts for AD9600ABCPZ-125
AD9600ABCPZ-125 Summary of contents
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FEATURES SNR = 60.6 dBc (61.6 dBFS MHz at 150 MSPS SFDR = 81 dBc to 70 MHz at 150 MSPS Low power: 825 mW at 150 MSPS 1.8 V analog supply operation 1 3.3 V ...
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AD9600 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications ..................................................................................... 5 DC Specifications ......................................................................... 5 AC Specifications .......................................................................... 6 Digital Specifications ...
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REVISION HISTORY 12/09—Rev Rev. B Added new models to Specifications Section ................................ 5 Changes to Table 7 .......................................................................... 12 Updated Outline Dimensions ........................................................ 71 Changes to Ordering Guide ........................................................... 72 6/09—Rev Rev. A Changes to Specifications ...
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AD9600 GENERAL DESCRIPTION The AD9600 is a dual, 10-bit, 105 MSPS/125 MSPS/150 MSPS ADC designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture ...
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... Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 8 for the equivalent analog input structure. 3 Standby power is measured with a dc input and the CLK+ and CLK− pins inactive )set to AVDD or AGND. AD9600ABCPZ-105/ AD9600ABCPZ-125/ AD9600BCPZ-105 AD9600BCPZ-125 Temp ...
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... ANALOG INPUT BANDWIDTH 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel. AD9600ABCPZ-105/ AD9600ABCPZ-125/ AD9600BCPZ-105 AD9600BCPZ-125 Temp Min Typ Max Min 25° ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance ...
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AD9600 Parameter LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN) High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 3.3 V) Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V High ...
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... OUT-OF-RANGE RECOVERY TIME Full 1 Output propagation delay is measured from the CLK+ and CLK− pins 50% transition to the output data pins 50% transition, with 5 pF load. 2 Wake-up time is dependent on the value of the decoupling capacitors. AD9600ABCPZ-105/ AD9600ABCPZ-125/ AD9600BCPZ-105 AD9600BCPZ-125 Min Typ Max Min Typ ...
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AD9600 TIMING CHARACTERISTICS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t Setup time between SYNC and the rising edge of CLK+ SSYNC t Hold time between SYNC and the rising edge of CLK+ HSYNC SPI TIMING REQUIREMENTS t Setup time ...
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CLK+ CLK– CH A/CH B DATA A CH A/CH B FAST A DETECT DCO+ DCO– Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000) CLK+ SYNC CLK+ CLK– t CSSCLK SMI SCLK/PDWN ...
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AD9600 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter ELECTRICAL AVDD, DVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD VIN + A/VIN + B, VIN − A/VIN − AGND CLK+, CLK− to AGND SYNC to AGND ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DRVDD (MSB) D9B DCOB DCOA (LSB) D0A NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD ...
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AD9600 Pin No. Mnemonic ADC Fast Detect Outputs 29 FD0A 30 FD1A 31 FD2A 32 FD3A 53 FD0B 54 FD1B 55 FD2B 56 FD3B Digital Inputs 52 SYNC Digital Outputs D0A to D9A 16 to 19, 22, 23 ...
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DRVDD DNC DNC DNC DNC DNC DNC (LSB) D0– DCO– DCO+ NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST ...
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AD9600 Pin No. Mnemonic ADC Fast Detect Outputs 54 FD0+ 53 FD0− 56 FD1+ 55 FD1− 59 FD2+ 58 FD2− 61 FD3+ 60 FD3− Digital Inputs 52 SYNC Digital Outputs 9 D0+ 8 D0− 13 D1+ 12 D1− 15 D2+ ...
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EQUIVALENT CIRCUITS VIN Figure 8. Analog Input Circuit AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 9. Equivalent Clock Input Circuit DRVDD DRGND Figure 10. Digital Output DRVDD DVDD 26kΩ 1kΩ SDIO/DCS Figure 11. Equivalent SDIO/DCS Input Circuit CLK– DVDD DRVDD Rev. ...
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AD9600 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, sample rate = 150 MSPS, DCS enabled internal reference p-p differential input, VIN = −1.0 dBFS, 64k sample, and T ...
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SNR = 60.0dB (61.0dBFS) –20 ENOB = 9.6 BITS SFDR = 70.0dBc –40 SECOND HARMONIC –60 THIRD HARMONIC –80 –100 –120 FREQUENCY (MHz) Figure 22. AD9600-150 Single-Tone FFT with ...
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AD9600 120 100 SFDR (dBFS) SNR (dBFS 85dB REFERENCE LINE 40 SFDR (dBc) 20 SNR (dBc) 0 –60 –50 –40 –30 AMPLITUDE (dBm) Figure 28. AD9600-150 Single-Tone SNR/SFDR vs. Input Amplitude ( 2.4 MHz IN 100 ...
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SFDR (dBc) –20 –40 IMD3 (dBc) –60 SFDR (dBFS) –80 IMD3 (dBFS) –100 –120 –60 –48 –36 INPUT AMPLITUDE (dBFS) Figure 34. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Amplitude ( 169.1 MHz 172.1 MHz, f IN1 ...
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AD9600 – – – OUTPUT CODE Figure 40. AD9600 Grounded Input Histogram 0.10 0.05 0 –0.05 –0.10 0 128 256 384 512 640 OUTPUT CODE Figure ...
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THEORY OF OPERATION The AD9600 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog ...
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AD9600 ADC. The output common-mode voltage of the easily set with the CML pin of the AD9600 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to band limit the input signal. 1V p-p 49.9Ω ...
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VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9600. The input range can be adjusted by varying the reference voltage applied to the AD9600, using either the internal reference or an externally applied reference voltage. The ...
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AD9600 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve the thermal drift characteristics. Figure 54 shows the typical drift characteristics of the internal reference in ...
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In some applications acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a ...
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AD9600 POWER DISSIPATION AND STANDBY MODE As shown in Figure 63, the power dissipated by the AD9600 is proportional to its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of the digital ...
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Table 12. SCLK/DFS Mode Selection (External Pin Mode) Voltage at Pin SCLK/DFS AGND Offset binary (default) AVDD Twos complement Digital Output Enable Function (OEB) The AD9600 has a flexible three-state ability for the digital output pins. The three-state mode can ...
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AD9600 ADC OVERRANGE AND GAIN CONTROL In receiver applications desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides after-the-fact infor- mation on the state of the ...
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When the fast detect mode select bits are set to 0b001, 0b010, or 0b011, a subset of the fast detect output pins is available. In these modes, the fast detect output pins have a latency of six clock cycles. Table ...
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AD9600 Increment Gain (IG) and Decrement Gain (DG) The increment gain and decrement gain indicators are intended to be used together to provide information to enable external gain control. The decrement gain indicator works in conjunction with the coarse upper ...
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SIGNAL MONITOR The signal monitoring block provides additional information about the signal being digitized by the ADC. The signal monitor computes the rms input magnitude, the peak magnitude, and/or the number of samples by which the magnitude exceeds a particular ...
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AD9600 the value of the accumulator is reset to the first input sample signal power, and the accumulation continues with the subsequent input samples. Figure 68 illustrates the rms magnitude monitoring logic. FROM MEMORY MAP SIGNAL MONITOR DOWN PERIOD REGISTER ...
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DC CORRECTION Because the dc offset of the ADC may be significantly larger than the signal being measured correction circuit is included to null the dc offset before measuring the power. The dc correction circuit can also be ...
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AD9600 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9600 includes built-in test features to enable verification of the integrity of each channel as well as to facilitate board level debugging. A BIST feature is included that verifies the integrity of ...
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CHANNEL/CHIP SYNCHRONIZATION The AD9600 has a SYNC input that offers the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful to guarantee synchronized sample clocks across multiple ADCs. The signal monitor block can ...
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AD9600 SERIAL PORT INTERFACE (SPI) The AD9600 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This may provide the user with additional flexibility and customization, depending ...
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CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin, and the SMI SCLK/PDWN pin serve as standalone CMOS- compatible control pins. When the device ...
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AD9600 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map registers table (Table 22) has eight bit locations. The memory map is divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02), the ...
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MEMORY MAP All address and bit locations that are not included in Table 22 are currently not supported for this device. Table 22. Memory Map Registers Addr Register Bit 7 (Hex) Name (MSB) Bit 6 Chip Configuration Registers 0x00 SPI ...
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AD9600 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0E BIST Enable Open Open (Local) 0x10 Offset Adjust Open Open (Local) 0x14 Output Mode Drive Output type strength 0 = CMOS 3 LVDS ...
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Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x10A Increase Gain Dwell Time Register 0 (Local) 0x10B Increase Gain Dwell Time Register 1 (Local) 0x10C Signal Monitor Open DC DC Correction correction Control freeze (Global) 0x10D Signal Monitor DC ...
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AD9600 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x118 Signal Monitor Open Open Result Channel A Register 2 (Global) 0x119 Signal Monitor Result Channel B Register 0 (Global) 0x11A Signal Monitor Result Channel B Register 1 (Global) 0x11B ...
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Increase Gain Dwell Time (Register 0x10A and Register 0x10B) Register 0x10A, Bits [7:0]—Increase Gain Dwell Time [7:0] Register 0x10B, Bits [7:0]—Increase Gain Dwell Time [15:8] These registers are programmed with the dwell time in ADC clock cycles. The signal must ...
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AD9600 Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits [7:0]—Signal Monitor Period [7:0] Register 0x114, Bits [7:0]—Signal Monitor Period [15:8] Register 0x115, Bits [7:0]—Signal Monitor Period [23:16] This 24-bit value sets the number of clock cycles over ...
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APPLICATIONS INFORMATION DESIGN GUIDELINES When designing the AD9600 into a system, the designer should, before starting design and layout, become familiar with these guidelines, which discuss the special circuit connections and layout requirements for certain pins. Power and Ground Recommendations ...
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AD9600 EVALUATION BOARD The AD9600 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially using the double-balun configuration (default AD8352 differential driver. ...
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DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings, or modes, allowed on the AD9600 evaluation board. POWER Connect the switching power supply that is provided with the evaluation kit between a ...
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AD9600 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION This section provides a brief description of the alternative analog input drive configuration using the AD8352. When using this drive option, some additional components need to be populated. For more details on the AD8352 ...
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SCHEMATICS 10KOHM R41 24.9OHM R29 100OHM R127 K 4.12 R126 DNP R36 24.9OHM R35 F Figure 74. Evaluation Board Schematic, Channel A Analog Inputs Rev Page AD9600 06909-301 57.6OHM R5 33OHM 33OHM R43 R47 OHM ...
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AD9600 10KOHM R53 AMPVDD 24.9OHM 100OHM R129 K 4.12 R128 DNP R68 24.9OHM R134 R135 F Figure 75. Evaluation Board Schematic, Channel B Analog Inputs Rev Page 06909-302 57.6OHM R72 33OHM 33OHM R70 R71 OHM ...
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R85 R82 OHM 0 R8 Figure 76. Evaluation Board Schematic, DUT Clock Input Rev Page TP2 24.9OHM 1 2 R83 DNP R34 F 57.6OHM 57.6OHM R30 AD9600 06909-303 ...
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AD9600 100OHM R9 49 VS_OUT67_1 50 VS_OUT67_2 51 VS_OUT01_DIV 52 OUT1B 53 OUT1 54 VS_OUT01_DRV 55 OUT0B 56 OUT0 57 VS_REF K 4.12 58 RSET_CLOCK R12 59 GND_REF 60 R VS_PRESCALE 61 VS_PLL_2 K 5.1 62 CP_RSET R11 63 REFINB ...
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RES040 10KOHM R105 2 RES040 10KOHM R103 2 RES040 10KOHM R102 2 RES040 10KOHM R100 10KOHM 10KOHM 24.9OHM R87 TP1 RES060 57.6OHM R45 2 Figure 78. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC ...
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AD9600 RPAK8 22ohm A FD0 FD1 FD2 FD3 4 13 PWR_SDO PWR_SCL PWR_SDFS RES040 OHM 0 R112 D1A D2A 19 D3A ...
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RES040 10KOHM R118 VAL R130 2 RES040 10KOHM R140 Figure 80. Evaluation Board Schematic, Digital Output Interface Rev Page AD9600 06909-307 100OHM R77 ...
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AD9600 Figure 81. Evaluation Board Schematic, SPI Circuitry Rev Page 06909-308 RES0402 10KOHM R65 ...
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M 140KOH R13 GND RES060 261OHM A C R16 CR7 2 1 S2A_REC T SJ35 Figure 82. Evaluation Board Schematic, Power Supply Rev Page 78.7KOH R14 1 TP25 AD9600 06909-309 ...
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AD9600 4 SJ36 GND 4 1 GND 1 SJ37 M 140KOH R25 GND 4 1 Figure 83. Evaluation Board Schematic, Power Supply (Continued) Rev Page 06909-310 M 78.7KOH R15 ...
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EVALUATION BOARD LAYOUTS Figure 84. Evaluation Board Layout, Primary Side Rev Page AD9600 ...
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AD9600 Figure 85. Evaluation Board Layout, Ground Plane Rev Page ...
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Figure 86. Evaluation Board Layout, Power Plane Rev Page AD9600 ...
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AD9600 Figure 87. Evaluation Board Layout, Power Plane Rev Page ...
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Figure 88. Evaluation Board Layout, Ground Plane Rev Page AD9600 ...
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AD9600 Figure 89. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page ...
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Figure 90. Evaluation Board Layout, Silkscreen, Primary Side Rev Page AD9600 ...
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AD9600 Figure 91. Evaluation Board Layout, Silk Screen, Secondary Side Rev Page ...
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BILL OF MATERIALS Table 23. Evaluation Board Bill of Materials (BOM) Reference Item Qty Designator Description 1 1 AD9600CE_REVB PCB C3, C6, C7, 0.1 μ ceramic C13, C14, C17, C18, capacitor, SMT 0402 C20 ...
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AD9600 Reference Item Qty Designator Description 26 1 R16 261 Ω, 0603, 1/ resistor 27 3 R17, R22, R23 100 kΩ, 0603, 1/ resistor 28 7 R18, R24, R63, R65, 10 kΩ, 0402, 1/16 W, R82, ...
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OUTLINE DIMENSIONS PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 BSC BSC SQ 0.50 33 ...
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... AD9600 ORDERING GUIDE Model Temperature Range 1,2 AD9600ABCPZ-150 −40°C to +85°C 1,2 AD9600ABCPZ-125 −40°C to +85°C AD9600ABCPZ-105 1,2 −40°C to +85°C 1 AD9600BCPZ-150 −40°C to +85°C AD9600BCPZ-125 1 −40°C to +85°C 1 AD9600BCPZ-105 −40°C to +85°C 1 AD9600-150EBZ RoHS Compliant Part. ...