AD9609BCPZ-20 Analog Devices Inc, AD9609BCPZ-20 Datasheet
AD9609BCPZ-20
Specifications of AD9609BCPZ-20
Related parts for AD9609BCPZ-20
AD9609BCPZ-20 Summary of contents
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FEATURES 1.8 V analog supply operation 1 3.3 V output supply SNR 61.5 dBFS at 9.7 MHz input 61.0 dBFS at 200 MHz input SFDR 75 dBc at 9.7 MHz input 73 dBc at 200 MHz input Low ...
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AD9609 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ...
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GENERAL DESCRIPTION The AD9609 is a monolithic, single channel 1.8 V supply, 10-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and- hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture ...
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AD9609 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 1. Parameter ...
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AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE ...
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AD9609 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL ...
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SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 4. Parameter CLOCK INPUT ...
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AD9609 TIMING SPECIFICATIONS Table 5. Parameter Conditions SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK DH t Period of the ...
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ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to AGND DRVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/PDWN to ...
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AD9609 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 8. Pin Function Descriptions Pin No. Mnemonic Description 0 (Exposed Pad) AGND The exposed paddle is the only ground connection. It must be soldered to the analog ground of the PCB to ensure ...
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TYPICAL PERFORMANCE CHARACTERISTICS AD9609-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 80MSPS 9.7MHz ...
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AD9609 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted SFDR (dBc ...
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AD9609-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted 65MSPS 9.7MHz @ –1dBFS ...
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AD9609 AD9609-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 40MSPS 9.7MHz @ –1dBFS ...
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AD9609-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 20MSPS 9.7MHz @ –1dBFS –20 ...
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AD9609 EQUIVALENT CIRCUITS AVDD VIN± Figure 26. Equivalent Analog Input Circuit AVDD VREF 7.5kΩ Figure 27. Equivalent VREF Circuit AVDD 375Ω SENSE Figure 28. Equivalent SENSE Circuit 5Ω CLK+ 15kΩ 15kΩ 5Ω CLK– Figure 29. Equivalent Clock Input Circuit 375Ω ...
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THEORY OF OPERATION The AD9609 architecture consists of a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 10-bit result in ...
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AD9609 Differential Input Configurations Optimum performance is achieved while driving the AD9609 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode ...
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VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD9609. The VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are ...
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AD9609 CLOCK INPUT CONSIDERATIONS For optimum performance, clock the AD9609 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased ...
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Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty ...
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AD9609 POWER DISSIPATION AND STANDBY MODE As shown in Figure 53, the analog core power dissipated by the AD9609 is proportional to its sample rate. The digital power dissipation of the CMOS outputs are determined primarily by the strength of ...
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TIMING The AD9609 provides latched data with a pipeline delay of eight clock cycles. Data outputs are available one propagation delay (t ) after the rising edge of the clock signal. PD Minimize the length of the output data lines ...
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AD9609 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9609 includes a built-in test feature designed to enable verification of the integrity of each channel as well as to facili- tate board level debugging. A built-in self-test (BIST) feature that verifies ...
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SERIAL PORT INTERFACE (SPI) The AD9609 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, ...
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AD9609 HARDWARE INTERFACE The pins described in Table 14 constitute the physical interface between the programming device of the user and the serial port of the AD9609. The SCLK pin and the CSB pin function as inputs when using the ...
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MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table (see Table 17) contains eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address ...
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AD9609 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Addr Bit 7 (Hex) Register Name (MSB) Bit 6 Chip Configuration Registers 0x00 SPI ...
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Addr Bit 7 (Hex) Register Name (MSB) Bit 6 0x0E BIST enable Open Open 0x10 Offset adjust 8-bit device offset adjustment, Bits[7:0] (local) Offset adjust in LSBs from +127 to −128 (twos complement format) 0x14 Output mode 00 = 3.3 ...
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AD9609 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. USR2 (Register 0x101) Bit 3—Enable GCLK Detect Normally set high, this ...
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APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9609 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power ...
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... AD9609BCPZ-65 –40°C to +85° AD9609BCPZRL7-65 –40°C to +85° AD9609BCPZ-40 –40°C to +85° AD9609BCPZRL7-40 –40°C to +85° AD9609BCPZ-20 –40°C to +85° AD9609BCPZRL7-20 –40°C to +85°C 1 AD9609-80EBZ AD9609-65EBZ 1 1 AD9609-40EBZ 1 AD9609-20EBZ RoHS Compliant Part. ...