AD9627-125EBZ Analog Devices Inc, AD9627-125EBZ Datasheet
AD9627-125EBZ
Specifications of AD9627-125EBZ
Related parts for AD9627-125EBZ
AD9627-125EBZ Summary of contents
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... DCS, power-down, test modes, and voltage reference mode. 7. Pin compatibility with the AD9640, AD9627-11, and AD9600 for a simple migration from 12 bits to 14 bits, 11 bits bits. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...
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... Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications ..................................................................................... 5 ADC DC Specifications—AD9627-80/AD9627-105 .................. 5 ADC DC Specifications—AD9627-125/AD9627-150 ................ 6 ADC AC Specifications—AD9627-80/AD9627-105 ................... 7 ADC AC Specifications—AD9627-125/AD9627-150 ................. 8 Digital Specifications ................................................................... 9 Switching Specifications—AD9627-80/AD9627-105 ................ 11 Switching Specifications—AD9627-125/AD9627-150 .............. 12 Timing Specifications ................................................................ 13 Absolute Maximum Ratings .......................................................... 15 Thermal Characteristics ............................................................ 15 ESD Caution ................................................................................ 15 Pin Configurations and Function Descriptions ......................... 16 Equivalent Circuits ...
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... REVISION HISTORY 5/10—Rev Rev. B Deleted CP-64-3 Package .................................................. Universal Added CP-64-6 Package .................................................... Universal Changed AD9627BCPZ-80 to AD9267-80 and AD9627BCPZ-105 to AD9627-105 Throughout .......................... 5 Changed AD9627BCPZ-125 to AD9267-125 and AD9627BCPZ-150 to AD9627-150 Throughout .......................... 6 Changes to Figure 6 ......................................................................... 16 Changes to Figure 7 ......................................................................... 18 Updated Outline Dimensions ........................................................ 74 Changes to Ordering Guide ........................................................... 74 6/09—Rev Rev. A Changes to Table 6 ...
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... CMOS or 1.8 V LVDS. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface. The AD9627 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. Rev Page ...
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... SPECIFICATIONS ADC DC SPECIFICATIONS—AD9627-80/AD9627-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes ...
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... AD9627 ADC DC SPECIFICATIONS—AD9627-125/AD9627-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 2. Parameter RESOLUTION ACCURACY No Missing Codes ...
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... ADC AC SPECIFICATIONS—AD9627-80/AD9627-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 3. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR 2.3 MHz ...
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... AD9627 ADC AC SPECIFICATIONS—AD9627-125/AD9627-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 4. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR ...
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... Full Full Full Full Full Full Full Full Full Full 1 Full Full Full Full Full Full 2 Full Full Full Full Rev Page AD9627 Min Typ Max CMOS/LVDS/LVPECL 1.2 0.2 6 GND − 0.3 AVDD + 1.6 1.1 AVDD 1.2 3.6 0 0.8 −10 +10 −10 + ...
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... AD9627 Parameter Input Resistance Input Capacitance DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V High Level Output Voltage μ 0 Low Level Output Voltage μA OL CMOS Mode—DRVDD = 1.8 V High Level Output Voltage μ 0 Low Level Output Voltage μA OL LVDS Mode—DRVDD = 1.8 V ...
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... SWITCHING SPECIFICATIONS—AD9627-80/AD9627-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 6. Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate 1 DCS Enabled 1 DCS Disabled CLK Period—Divide-by-1 Mode (t ...
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... AD9627 SWITCHING SPECIFICATIONS—AD9627-125/AD9627-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 7. Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate 1 DCS Enabled DCS Disabled 1 CLK Period— ...
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... Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000 CLK – – – – – – – DCO Rev Page Min Typ Max 0.24 0. 3.2 4.5 6.2 −0.4 0 0.4 −0 – – – – CLK AD9627 Unit ...
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... AD9627 CLK+ CLK– CH A/CH B DATA A N – A/CH B FAST A DETECT N – 7 DCO+ DCO– Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through Fast Detect Mode Select Bits = 100) CLK+ SYNC CLK+ CLK– ...
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... Rev Page Airflow Velocity (m/s) θ θ 18.8 0.6 1.0 16.5 2.0 15.8 is specified for a 4-layer PCB with a solid ground addition, metal in direct contact with the package AD9627 1, 4 θ Unit JB 6.0 °C/W °C/W °C/W ...
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... FD3B Output PIN 1 INDICATOR 1 D4B 2 D5B 3 D6B 4 EXPOSED PADDLE, PIN 0 D7B 5 (BOTTOM OF PACKAGE) D8B 6 D9B 7 D10B 8 AD9627 9 PARALLEL CMOS DCOB 10 TOP VIEW DCOA 11 (Not to Scale) DNC 12 DNC 13 14 D1A 15 D2A 16 NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND. ...
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... SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select (Active Low). Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. Signal Monitor Serial Data Frame Sync. Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode. Rev Page AD9627 ...
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... SYNC Input PIN 1 INDICATOR 1 DNC 2 DNC 3 4 EXPOSED PADDLE, PIN 0 5 (BOTTOM OF PACKAGE) D1– 6 D1+ 7 D2– 8 AD9627 D2+ 9 PARALLEL LVDS 10 TOP VIEW 11 D3– (Not to Scale) 12 D3+ 13 D4– 14 D4+ 15 D5– 16 NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND. ...
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... SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select (Active Low). Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. Signal Monitor Serial Data Frame Sync. Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode. Rev Page AD9627 ...
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... AD9627 EQUIVALENT CIRCUITS VIN Figure 8. Equivalent Analog Input Circuit AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 9. Equivalent Clock Input Circuit DRVDD DRGND Figure 10. Digital Output DRVDD DRVDD 26kΩ 1kΩ SDIO/DCS Figure 11. Equivalent SDIO/DCS or SMI SDFS Circuit SCLK/DFS Figure 12. Equivalent SCLK/DFS Input Circuit SENSE CLK– ...
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... ENOB = 11.2 BITS SFDR = 77.0dBc –40 –60 SECOND HARMONIC THIRD –80 HARMONIC –100 –120 FREQUENCY (MHz) Figure 20. AD9627-150 Single-Tone FFT with f 0 150MSPS 337MHz @ –1dBFS SNR = 67.6dBc (68.6dBFS) –20 ENOB = 11.1 BITS SFDR = 74.0dBc –40 –60 THIRD HARMONIC –80 –100 –120 ...
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... ENOB = 11.3 BITS SFDR = 84dBc –40 –60 SECOND –80 HARMONIC –100 –120 FREQUENCY (MHz) Figure 26. AD9627-125 Single-Tone FFT with f 0 125MSPS 337MHz @ –1dBFS SNR = 67.6dBc (68.6dBFS) –20 ENOB = 11.1 BITS SFDR = 74dBc –40 –60 THIRD –80 HARMONIC –100 –120 0 10 ...
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... SNR (dBFS SFDR (dBc) 85dB REFERENCE LINE 20 SNR (dBc) 0 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 28. AD9627-150 Single-Tone SNR/SFDR vs. Input Amplitude (A with f = 2.4 MHz IN 100 SFDR (dBFS) 80 SNR (dBFS) 60 SFDR (dBc) 40 85dB REFERENCE LINE 20 SNR (dBc) 0 –90 –80 – ...
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... IN1 –100 –120 –30 –18 – 150 MSPS S –100 –120 46.08 61.44 100 32.1 MHz Figure 39. AD9627-150 Single-Tone SNR/SFDR vs. Sample Rate (f IN2 Rev Page 150MSPS 169.1MHz @ –7dBFS 172.1MHz @ –7dBFS –20 SFDR = 83.8dBc (90.8dBFS) –40 –60 – FREQUENCY (MHz) Figure 37. AD9627-150 Two-Tone FFT with f = 169 ...
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... Figure 43. AD9627-150 SNR/SFDR vs. Duty Cycle with 3584 4096 0.2 Figure 44. AD9627-150 SNR/SFDR vs. Input Common Mode (VCM) 3584 4096 Rev Page SFDR DCS ON SFDR DCS OFF SNR DCS ON SNR DCS OFF 40 60 DUTY CYCLE (%) = 10.3 MHz IN SFDR SNR 0.3 0.4 0.5 0.6 ...
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... ADC core. The span of the ADC core is set by this buffer to 2 × VREF. Input Common Mode The analog inputs of the AD9627 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that V ...
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... The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9627 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 499Ω p-p 49.9Ω 499Ω C AD8138 0.1µF 523Ω ...
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... The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. If the internal reference of the AD9627 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 53 shows how the internal reference voltage is affected by loading ...
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... Jitter Considerations section. Figure 56 and Figure 57 show two preferred methods for clocking the AD9627 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun transformer. ...
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... RESISTOR IS OPTIONAL. Figure 61. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS) Input Clock Divider The AD9627 contains an input clock divider with the ability to divide the input clock by integer values between 1 and divide ratio other than 1 is selected, the duty cycle stabilizer is automatically enabled ...
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... POWER DISSIPATION AND STANDBY MODE As shown in Figure 63 through Figure 66, the power dissipated by the AD9627 is proportional to its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current (I ...
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... The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9627. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9627 is 10 MSPS. SDIO/DCS At clock rates below 10 MSPS, dynamic performance can degrade. ...
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... FAST DETECT OVERVIEW The AD9627 contains circuitry to facilitate fast overrange detec- tion, allowing very flexible external gain control implementations. Each ADC has four fast detect (FD) output pins that are used to output information about the current state of the ADC input level ...
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... ADC clock cycles. An overrange at the input is indicated by this bit 12 clock cycles after it occurs. GAIN SWITCHING The AD9627 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging converters are employed. This circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed ...
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... The operation of the increment gain output and the decrement gain output is shown in Figure 67. DWELL TIME TIMER RESET BY RISE ABOVE F_LT Figure 67. Threshold Settings for C_UT, F_UT, IG, DG, and F_LT Rev Page UPPER THRESHOLD (COARSE OR FINE) FINE LOWER THRESHOLD TIMER COMPLETES BEFORE DWELL TIME SIGNAL RISES ABOVE F_LT AD9627 ...
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... AD9627 SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the rms input magnitude, the peak magnitude, and/or the number of samples by which the magnitude exceeds a particular threshold. Together, these functions can be used to ...
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... GSM. Rev Page SIGNAL MONITOR DOWN IS COUNT = 1? PERIOD REGISTER COUNTER LOAD CLEAR LOAD SIGNAL MONITOR A COMPARE COMPARE HOLDING A > > B REGISTER (SMR) B UPPER THRESHOLD REGISTER Figure 70. ADC Input Threshold Crossing Block Diagram I AD9627 TO MEMORY MAP/SPORT ...
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... Register 0x10C, Bits[5:2] (values between 0 and 13 are valid for k; programming provides the same result as programming 13 the AD9627 ADC sample rate in hertz (Hz). CLK DC Correction Readback The current dc correction value can be read back in Register 0x10D and Register 0x10E for Channel A and Register 0x10F and Register 0x110 for Channel B ...
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... AD9627. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9627 signal path. When enabled, the test runs from an internal pseudorandom noise (PN) source through the digital datapath starting at the ADC block output. The BIST sequence runs for 512 cycles and stops ...
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... AD9627 CHANNEL/CHIP SYNCHRONIZATION The AD9627 has a SYNC input that offers the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful for guaranteeing synchro- nized sample clocks across multiple ADCs. The signal monitor block can also be synchronized using the SYNC input, allowing properties of the input signal to be measured during a specific time period ...
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... SERIAL PORT INTERFACE (SPI) The AD9627 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...
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... Table 24 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in Application Note AN-877, Interfacing to High Speed ADCs via SPI. The AD9627 part-specific features are described in detail following Table 25, the external memory map register table. Table 24. Features Accessible Using the SPI ...
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... Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD9627 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 25. Logic Levels An explanation of logic level terminology follows: ...
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... Open (Global) 0x0D Test Mode Open Open (Local) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit Chip ID[7:0] (AD9627 = 0x12) (default) Speed grade ID Open Open 00 = 150 MSPS 01 = 125 MSPS 10 = 105 MSPS MSPS Open Open Open Open Open Open Open ...
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... Open Open Fast Detect Mode Select[2:0] Open Open Open Coarse Upper Threshold[2:0] Fine Upper Threshold[7:0] Open Fine Upper Threshold[12:8] Fine Lower Threshold[7:0] Rev Page AD9627 Default Default Bit 0 Value Notes/ Bit 1 (LSB) (Hex) Comments Open BIST enable 0x00 0x00 ...
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... AD9627 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x109 Fine Lower Open Open Threshold Register 1 (Local) 0x10A Increase Gain Dwell Time Register 0 (Local) 0x10B Increase Gain Dwell Time Register 1 (Local) 0x10C Signal Monitor Open DC DC Correction correction Control freeze (Global) 0x10D ...
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... Register 0x109, Bits[4:0]—Fine Lower Threshold[12:8] These registers provide the fine lower limit threshold. This 13-bit value is compared with the 13-bit magnitude from the ADC block. If the ADC magnitude is less than this threshold value, the F_LT flag is set. Rev Page AD9627 Default Default Bit 0 Value Notes/ ...
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... Register 0x10C, Bits[5:2] (values between 0 and 13 are valid for k; programming provides the same result as programming 13 the AD9627 ADC sample rate in hertz (Hz). CLK Bit 1—DC Correction for Signal Path Enable Setting Bit 1 high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path ...
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... Register 0x11A, Bits[7:0]—Signal Monitor Result Channel B[15:8] Register 0x11B, Bits[7:4]—Reserved Register 0x11B, Bits[3:0]—Signal Monitor Result Channel B[19:16] This 20-bit value contains the result calculated by the signal monitoring block for Channel B. The result is dependent on the settings in Register 0x112[2:1]. Rev Page AD9627 ...
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... LVDS mode. This additional DRVDD current does not cause damage to the AD9627, but it should be taken into account when consid- ering the maximum DRVDD current for the part. To avoid this additional DRVDD current, the AD9627 outputs can be disabled at power-up by taking the OEB pin high ...
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... EVALUATION BOARD The AD9627 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configura- tions. The converter can be driven differentially through a double balun configuration (default) or optionally through the AD8352 differential driver. The ADC can also be driven in a single-ended fashion ...
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... The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. When the AD9627 input clock divider is utilized, clock frequencies up to 625 MHz can be input into the evaluation board through Connector S5. ...
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... Populate the optional amplifier output path with the desired components including an optional low-pass filter. Install 0 Ω resistors, R44 and R48. R43 and R47 should be increased (typically to 100 Ω) to increase to 200 Ω the output impedance seen by the AD8352. Rev Page AD9627 ...
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... AD9627 SCHEMATICS M OH 10K R41 100 R127 4.12K R126 DNP R36 24 24.9 R29 R35 F Figure 75. Evaluation Board Schematic, Channel A Analog Inputs Rev Page 06571-075 M OH 57.6 R5 OHM 33 OHM 33 R43 R47 OHM 57 57.6 R1 R28 2 2 ...
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... M OH 100 R129 4.12K R128 DNP R68 M OH 24.9 OHM 24.9 R134 R135 F Figure 76. Evaluation Board Schematic, Channel B Analog Inputs Rev Page 06571-076 M OH 57.6 R72 OHM 33 OHM 33 R70 R71 OHM 0 F R69 F OHM 57.6 OHM 57.6 R52 R51 2 2 AD9627 ...
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... AD9627 M OH 10K M OH 10K R85 R82 M OH 24.9 R83 57.6 R30 2 Figure 77. Evaluation Board Schematic, DUT Clock Input Rev Page 06571-077 TP2 1 2 DNP R34 ...
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... REFIN Figure 78. Evaluation Board Schematic, Optional AD9516 Clock Circuit Rev Page PAD 2 VS_OUT89_ 32 1 VS_OUT89_ 31 V VS_OUT45_DI 30 OUT5B 29 OUT5 28 VS_OUT45_DRV VS_OUT_DR 27 OUT4B 26 OUT4 25 PDB PDB 24 RESETB 23 SDIO SDI 22 SDO SDO 21 NC4 20 NC3 19 NC2 18 CSB CSB_2 17 OHM 49.9 R89 2 AD9627 06571-078 RESETB ...
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... AD9627 TP1 AC Figure 79. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input 2 RES040 M OH 10K R105 2 RES040 M OH 10K R103 2 RES040 M OH 10K R102 2 RES040 M OH 10K 2 RES040 R100 M OH 10K R107 2 RES040 M OH 10K R106 M OH 24.9 R87 1 3 RES060 ...
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... D4A 19 D5A 20 DRGND 1 21 DRVDD 1 22 D6A 23 D7A 24 DVDD1 25 D8A 26 D9A 27 D10A 28 D11A_MSB _ 29 FD0A 30 FD1A 31 FD2A 32 FD3A Figure 80. Evaluation Board Schematic, DUT Rev Page AD9627 06571-080 64 DRGN D 63 D3B 62 D2B 61 D1B 60 D0B_LSB DVDD DVDD2 56 FD3B 55 FD2B 54 FD1B 53 FD0B 52 SYNC C SYN ...
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... AD9627 M OH 10K R118 2 RES040 VAL R130 2 RES040 M OH 10K R140 Figure 81. Evaluation Board Schematic, Digital Output Interface Rev Page 06571-081 M OH 100 R77 ...
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... Figure 82. Evaluation Board Schematic, SPI Circuitry Rev Page AD9627 06571-082 RES0402 OHM 10K R65 ...
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... AD9627 2 M KOH 140 R13 GND 4 1 RES0603 M OH 261 A C R16 CR7 SJ35 1 S2A_REC T Figure 83. Evaluation Board Schematic, Power Supply Rev Page 06571-083 M KOH 78.7 R14 1 TP25 ...
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... SJ37 SJ36 Figure 84. Evaluation Board Schematic, Power Supply (Continued) M KOH 140 M KOH 78 Rev Page AD9627 06571-084 ...
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... AD9627 EVALUATION BOARD LAYOUTS Figure 85. Evaluation Board Layout, Primary Side Rev Page ...
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... Figure 86. Evaluation Board Layout, Ground Plane Rev Page AD9627 ...
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... AD9627 Figure 87. Evaluation Board Layout, Power Plane Rev Page ...
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... Figure 88. Evaluation Board Layout, Power Plane Rev Page AD9627 ...
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... AD9627 Figure 89. Evaluation Board Layout, Ground Plane Rev Page ...
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... Figure 90. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page AD9627 ...
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... AD9627 Figure 91. Evaluation Board Layout, Silkscreen, Primary Side Rev Page ...
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... Figure 92. Evaluation Board Layout, Silkscreen, Secondary Side Rev Page AD9627 ...
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... AD9627 BILL OF MATERIALS Table 26. Evaluation Board Bill of Materials (BOM) Reference Item Qty Designator Description 1 1 AD9627CE_REVB PCB C3, C6, C7, 0.1 μ ceramic C13, C14, C17, C18, capacitor, SMT 0402 C20 to C26, C32, C57 to C61, C65 to C76, C81 to C83, C96 to C101, C103, C105, C107, ...
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... R76 200 Ω, 0402, 1/ resistor 34 4 S2, S3, S5 ,S12 SMA, inline, male, coaxial connector 35 1 SJ35 0 Ω, 1 resistor Balun IC, AD9627 Clock distribution, PLL Dual inverter Dual buffer IC, open-drain circuits UHS dual buffer U15 to U17 16-bit CMOS buffer IC 43 ...
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... PLANE ORDERING GUIDE 1 Model Temperature Range AD9627ABCPZ-150 −40°C to +85°C AD9627ABCPZ-125 −40°C to +85°C AD9627ABCPZ-105 −40°C to +85°C AD9627ABCPZ-80 −40°C to +85°C AD9627-150EBZ AD9627-125EBZ RoHS Compliant Part. 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 BSC BSC SQ 0. ...
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... NOTES Rev Page AD9627 ...
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... AD9627 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06571-0-5/10(B) Rev Page ...