AD9640-125EBZ Analog Devices Inc, AD9640-125EBZ Datasheet
AD9640-125EBZ
Specifications of AD9640-125EBZ
Related parts for AD9640-125EBZ
AD9640-125EBZ Summary of contents
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... Pin compatibility with the AD9627, AD9627-11, and the AD9600 for a simple migration from 14 bits to 12 bits, 11 bits bits. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved. AD9640 SDIO/ SCLK/ DCS DFS CSB DRVDD SPI ...
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... AD9640BCPZ-105 ......................................................................... 5 ADC DC Specifications—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, and AD9640BCPZ-150 ......................................................................... 6 ADC AC Specifications—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, and AD9640BCPZ-105 ......................................................................... 7 ADC AC Specifications—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, and AD9640BCPZ 150 ......................................................................... 8 Digital Specifications ................................................................... 9 Switching Specifications—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, and AD9640BCPZ-105 ..................................................................... 10 Switching Specifications—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, and AD9640BCPZ-150 ..................................................................... 11 Timing Specifications ................................................................ 12 Absolute Maximum Ratings ...
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... Change to Table 15 .......................................................................... 30 Changes to ADC Overrange and Gain Control Section ............ 31 Changes to Signal Monitor Section .............................................. 34 Changes to Table 25 ........................................................................ 42 Changes to Signal Monitor Period (Register 0x113 to Register 0x115) Section .................................................................. 47 Added LVDS Operation Section ................................................... 48 Added Exposed Pad Notation to Outline Dimensions .............. 49 6/07—Revision 0: Initial Version Rev Page AD9640 ...
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... CMOS or 1.8 V LVDS. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface. The AD9640 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. Rev Page ...
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... SPECIFICATIONS ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 1. Parameter RESOLUTION ...
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... AD9640 ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 2. Parameter RESOLUTION ...
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... ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 3. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR ...
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... AD9640 ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ 150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 4. 1 Parameter ...
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... Full Full Full Full Full Full Full Full 1 Full Full Full Full Full Full 2 Full Full Full Full Full Full Rev Page AD9640 Min Typ Max CMOS/LVDS/LVPECL 1.2 0.2 6 AGND − 0.3 AVDD + 1.6 1.1 AVDD 1.2 3.6 0 0.8 −10 +10 −10 + ...
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... Reduced Swing Mode OS 1 Pull up. 2 Pull down. SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 6. Parameter CLOCK INPUT PARAMETERS ...
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... Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors. SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150 AVDD = 1.8 V, DVDD = 1.8V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted ...
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... AD9640 TIMING SPECIFICATIONS Table 8. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time SSYNC t SYNC to rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK ...
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... A N – – – – – – – – – – DCO t t SSYNC HSYNC Figure 4. SYNC Input Timing Requirements t SSCLKSDO DATA Figure 5. Signal Monitor SPORT Output Timing (Divide by 2 Mode) Rev Page – – – – – CLK DATA AD9640 ...
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... AD9640 ABSOLUTE MAXIMUM RATINGS Table 9. Parameter ELECTRICAL AVDD, DVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND CML to AGND RBIAS to AGND CSB to AGND SCLK/DFS to DRGND SDIO/DCS to DRGND ...
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... Differential Analog Input Pin (−) for Channel B. Voltage Reference Input/Output. Voltage Reference Mode Select. See Table 14 for details. External Reference Bias Resistor. Common Mode Level Bias Output for Analog Inputs. ADC Clock Input—True. ADC Clock Input—Complement. Rev Page AD9640 48 SCLK/DFS 47 SDIO/DCS 46 AVDD 45 ...
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... AD9640 Pin No. Mnemonic Type ADC Fast Detect Outputs 29 FD0A Output 30 FD1A Output 31 FD2A Output 32 FD3A Output 53 FD0B Output 54 FD1B Output 55 FD2B Output 56 FD3B Output Digital Inputs 52 SYNC Input Digital Outputs 12 D0A (LSB) Output 13 D1A Output 14 D2A Output 15 D3A Output 16 D4A Output ...
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... Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 18 for details. Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 18 for details. Rev Page SCLK/DFS 47 SDIO/DCS 46 AVDD 45 AVDD 44 VIN+B 43 VIN–B 42 RBIAS 41 CML 40 SENSE 39 VREF 38 VIN–A 37 VIN+A 36 AVDD 35 SMI SDFS 34 SMI SCLK/PDWN 33 SMI SDO/OEB AD9640 ...
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... AD9640 Pin No. Mnemonic Type Digital Inputs 52 SYNC Input Digital Outputs 63 D0+ (LSB) Output 62 D0− (LSB) Output 3 D1+ Output 2 D1− Output 5 D2+ Output 4 D2− Output 7 D3+ Output 6 D3− Output 9 D4+ Output 8 D4− Output 13 D5+ Output 12 D5− ...
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... Figure 10. Digital Output DRVDD DVDD 26kΩ 1kΩ SDIO/DCS Figure 11. Equivalent SDIO/DCS or SMI SDFS Circuit CLK– DVDD DRVDD Rev Page AD9640 DVDD 1kΩ SCLK/DFS 26kΩ Figure 12. Equivalent SCLK/DFS Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit DVDD DVDD 26kΩ ...
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... SNR = 70dBc (71dBFS) –20 ENOB = 11.5 BITS SFDR = 80dBc –40 SECOND HARMONIC –60 THIRD HARMONIC – FREQUENCY (MHz) Figure 20. AD9640-150 Single-Tone FFT with 150MSPS 337MHz @ –1dBFS SNR = 68dBc (69dBFS) –20 ENOB = 11 BITS SFDR = 72.4dB –40 THIRD HARMONIC –60 SECOND HARMONIC – ...
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... MHz Figure 25. AD9640-125 Single-Tone FFT with –20 –40 –60 –80 –100 –120 2.3 MHz Figure 26. AD9640-125 Single-Tone FFT with –20 –40 –60 –80 –100 –120 30.3 MHz Figure 27. AD9640-125 Single-Tone FFT with f IN Rev Page 125MSPS 70MHz @ –1dBFS SNR = 71.8dBc (72.8dBFS) ENOB = 11 ...
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... Temperature with 2 V p-p Full Scale IN SNR (dBc) –30 –20 – SNR (dBc) –30 –20 –10 0 SFDR = –40°C 300 350 400 450 Figure 33. AD9640-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A Rev Page SFDR = +25° SFDR = +85°C SNR = –40° SNR = +25°C SNR = +85° 100 150 ...
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... SFDR (dBc) –40 –60 IMD3 (dBc) IMD3 (dBFS) –80 SFDR (dBFS) –100 –120 –90 –78 –66 –54 –42 INPUT AMPLITUDE (dBFS) Figure 34. AD9640-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f = 169.1 MHz 172.1 MHz, f IN1 IN2 0 –20 –40 –60 –80 –100 –120 0 15.36 30 ...
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... OUTPUT CODE Figure 42. AD9640 DNL with f IN 1.3 LSB rms 16,384 = 10.3 MHz Figure 44. AD9640 SNR/SFDR vs. Input Common Mode Voltage (VCM) 16,384 = 10.3 MHz Rev Page 100 SFDR DCS SFDR DCS OFF 80 SNR DCS ON ...
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... THEORY OF OPERATION The AD9640 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any f ...
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... AD9640 The output common-mode voltage of the with the CML pin of the AD9640 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 499Ω p-p 49.9Ω 499Ω AD8138 C 0.1µF 523Ω ...
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... VREF Programmable Reference 0 VREF Internal Fixed Reference AGND to 0 the internal reference of the AD9640 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 53 shows how the internal reference voltage is affected by loading. ADC CORE ...
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... Jitter Considerations section. Figure 56 and Figure 57 show two preferred methods for clocking the AD9640 (at clock rates to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun transformer. The RF balun ...
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... IF undersampling applications are particularly sensitive to jitter, as illustrated in Figure 62. The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9640. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise ...
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... DRVDD DRVDD LOAD CLK where N is the number of output bits (30 in the case of the AD9640 with the FD bits disabled). This maximum current occurs when every output bit switches on every clock cycle, that is, a full- scale square wave at the Nyquist frequency of f the DRVDD current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal ...
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... VIN+ − VIN− > +VREF − 0.5 LSB Digital Output Enable Function (OEB) The AD9640 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the SMI SDO/OEB pin or through the SPI interface. If the SMI SDO/OEB pin is low, the output data drivers are enabled ...
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... FAST DETECT OVERVIEW The AD9640 contains circuitry to facilitate fast overrange detec- tion, allowing very flexible external gain control implementations. Each ADC has four fast detect (FD) output pins that are used to output information about the current state of the ADC input level ...
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... ADC clock cycles. An overrange at the input is indicated by this bit 12 clock cycles after it occurs. GAIN SWITCHING The AD9640 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging converters are employed. This circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed ...
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... AD9640 similarly, corresponds to the fine lower threshold bits, except that it is asserted only if the input magnitude is less than the value programmed in the fine lower threshold register after the dwell time elapses. The dwell time is set by the 16-bit dwell time value located at Address 0x10A and Address 0x10B and is set in units of ADC input clock cycles ranging from 1 to 65,535 ...
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... The monitor period timer is reloaded with the value in the SMPR, and the countdown is restarted. In addition, the first input sample signal power is updated in the accumulator, and the accumulation continues with the subsequent input samples. Rev Page AD9640 DOWN IS COUNT = 1? COUNTER LOAD TO ...
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... AD9640 Figure 69 illustrates the rms magnitude monitoring logic. FROM MEMORY MAP SIGNAL MONITOR DOWN PERIOD REGISTER COUNTER LOAD FROM CLEAR LOAD INPUT SIGNAL MONITOR PORTS ACCUMULATOR REGISTER (SMR) Figure 69. ADC Input RMS Magnitude Monitoring Block Diagram For rms magnitude mode, the value in the signal monitor result (SMR) register is a 20-bit fixed-point number ...
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... If enabled, the data is sent, rms first, followed by peak and threshold, as shown in Figure 71 MSB RMS/ THR CYCLES 16 CYCLES 20 CYCLES GATED, BASED ON CONTROL LSB THR CH A MSB RMS/ LSB 16 CYCLES 20 CYCLES Rev Page GATED, BASED ON CONTROL LSB THR CYCLES 16 CYCLES THR CYCLES AD9640 RMS/ RMS/ ...
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... BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9640 signal path. When enabled, the test runs from an internal PN source through the digital data path starting at the ADC block output. The BIST sequence runs for 512 cycles and stops. ...
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... CHANNEL/CHIP SYNCHRONIZATION The AD9640 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful to guarantee synchronized sample clocks across multiple ADCs. The signal monitor block can also be synchronized using the SYNC input allowing properties of the input signal to be measured during a specific time period ...
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... The pins described in Table 22 comprise the physical interface between the user’s programming device and the serial port of the AD9640. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...
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... A brief description of general features accessible via the SPI follows. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9640 part-specific features are described in detail following Table 25, the external memory map register table. Table 24. Features Accessible Using the SPI ...
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... AD9640 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight bit locations. The memory map is roughly divided into four sections: chip configura- tion and ID register map (Address 0x00 to Address 0x02); ADC setup, control, and test (Address 0x08 to Address 0x25); the channel index and transfer register map (Address 0x05 to Address 0xFF) ...
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... Open (Global) 0x0D Open Open Test Mode (Local) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit Chip ID[7:0] (AD9640 = 0x11) (default) Speed grade ID Open Open 00 = 150 MSPS 01 = 125 MSPS 10 = 105 MSPS MSPS Open Open Open Open Open Open Open ...
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... AD9640 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0E BIST Enable Open Open (Local) 0x10 Offset Adjust Open Open (Local) 0x14 Output Mode Drive Output type strength 0 = CMOS 3 LVDS CMOS or (global) ANSI LVDS 1.8 V CMOS or reduced: LVDS (global) 0x16 Clock Phase ...
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... Signal Monitor Period[7:0] Signal Monitor Period[15:8] Signal Monitor Period[23:16] Signal Monitor Result Channel A[7:0] Signal Monitor Result Channel A[15:8] Open Open Signal Monitor Value Channel A[19:16] Signal Monitor Result Channel B[7:0] Rev Page AD9640 Default Default Bit 0 Value Notes/ Bit 1 (LSB) (Hex) Comments ...
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... AD9640 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x11A Signal Monitor Result Channel B Register 1 (Global) 0x11B Signal Monitor Open Open Result Channel B Register 2 (Global) MEMORY MAP REGISTER DESCRIPTION For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI ...
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... This 24-bit value sets the number of clock cycles over which the signal monitor performs its operation. Although this register defaults to 64 (0x40), the minimum value for this register is 128 (0x80) cycles – writing values less than 128 can cause inaccurate results. Rev Page AD9640 2 ...
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... AD9640 Signal Monitor Result Channel A (Register 0x116 to Register 0x118) Register 0x116, Bits[7:0]—Signal Monitor Result Channel A[7:0] Register 0x117, Bits[7:0]—Signal Monitor Result Channel A[15:8] Register 0x118, Bits[7:4]—Reserved Register 0x118, Bits[3:0]—Signal Monitor Result Channel A[19:16] This 20-bit value contains the result calculated by the signal monitoring block for Channel A ...
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... LVDS mode. This additional DRVDD current does not cause damage to the AD9640, but it should be taken into account when consid- ering the maximum DRVDD current for the part. To avoid this additional DRVDD current, the AD9640 outputs can be disabled at power-up by taking the OEB pin high ...
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... AD9640 OUTLINE DIMENSIONS PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 BSC BSC SQ 0.50 0. 0.30 0.80 MAX 0.65 TYP 0.05 MAX ...
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... AD9640BCPZ-125 −40°C to +85°C 1 AD9640BCPZ-105 −40°C to +85°C 1 AD9640BCPZ-80 −40°C to +85°C 1 AD9640-150EBZ 1 AD9640-125EBZ 1 AD9640-105EBZ 1 AD9640-80EBZ RoHS Compliant Part. 2 Recommended for use in new designs; reference PCN 09_0156. Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] ...
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... AD9640 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06547-0-12/09(B) Rev Page ...