AD9650-105EBZ Analog Devices Inc, AD9650-105EBZ Datasheet
AD9650-105EBZ
Specifications of AD9650-105EBZ
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AD9650-105EBZ Summary of contents
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... Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9650 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. On-chip dither option for improved SFDR performance with low power analog input ...
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... Timing Specifications .................................................................. 8 Absolute Maximum Ratings.......................................................... 10 Thermal Characteristics ................................................................ 10 ESD Caution................................................................................ 10 Pin Configurations and Function Descriptions ......................... 11 Typical Performance Characteristics ........................................... 15 AD9650-25 .................................................................................. 15 AD9650-65 .................................................................................. 18 AD9650-80 .................................................................................. 21 AD9650-105 ................................................................................ 24 Equivalent Circuits ......................................................................... 28 Theory of Operation ...................................................................... 29 REVISION HISTORY 7/10—Revision 0: Initial Version ADC Architecture ...................................................................... 29 Analog Input Considerations ................................................... 29 Voltage Reference ....................................................................... 32 Channel/Chip Synchronization................................................ 34 Power Dissipation and Standby Mode .................................... 34 Digital Outputs ...
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... AD9650 Unit Bits % FSR % FSR LSB LSB LSB LSB % FSR % FSR ppm/°C ppm/° LSB rms V p kΩ ...
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... Rev Page AD9650BCPZ-80 AD9650BCPZ-105 Min Typ Max Min Typ Max 83 82 81.6 80 80.4 80.7 80 78.5 78.8 75.1 75.5 13.5 13.3 13.2 13.2 13.0 13.0 13 ...
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... Full 26 Full 2 Full 1.22 Full 0 Full −10 Full 38 Full 26 Full 5 Full 1.22 Full 0 Full −90 Full −10 Full 26 Full 5 Rev Page AD9650 Max Unit V 3.6 V p-p AVDD V 1.4 V +100 μA +100 μ kΩ V AVDD V AVDD V 0.6 V +100 μA +100 μ kΩ ...
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... AD9650 Parameter DIGITAL OUTPUTS CMOS Mode—DRVDD = 1.8 V High Level Output Voltage μ 0 Low Level Output Voltage μA OL LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (V ), ANSI Mode OD Output Offset Voltage (V ), ANSI Mode OS Differential Output Voltage (V ), Reduced Swing Mode OD Output Offset Voltage (V ...
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... AD9650 Max Unit 640 MHz 105 MSPS 105 MSPS ns 6. rms 4 4 +0.5 ns Cycles Cycles μs Cycles ...
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... AD9650 TIMING SPECIFICATIONS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK+ setup time SSYNC t SYNC to rising edge of CLK+ hold time HSYNC 1 SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK ...
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... N – CLK+ CLK– t DCO DCOA/DCOB t CH A/CH B DATA Figure 4. LVDS Mode Data Output Timing CLK+ t SSYNC SYNC Figure 5. SYNC Input Timing Requirements CLK t SKEW – – – – – – HSYNC Rev Page AD9650 – – – 8 ...
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... AD9650 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter 1 Electrical AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB PDWN D0A/D0B Through D15A/D15B to ...
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... Channel A CMOS Output Data (LSB). Output Channel A CMOS Output Data. Output Channel A CMOS Output Data. Output Channel A CMOS Output Data. Output Channel A CMOS Output Data. Output Channel A CMOS Output Data. Output Channel A CMOS Output Data. Rev Page AD9650 48 PDWN 47 OEB 46 CSB 45 SCLK/DFS 44 SDIO/DCS 43 ORA 42 ...
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... AD9650 Pin No. Mnemonic 33 D7A 34 D8A 35 D9A 36 D10A 38 D11A 39 D12A 40 D13A 41 D14A 42 D15A 43 ORA 4 D0B 5 D1B 6 D2B 7 D3B 8 D4B 9 D5B 11 D6B 12 D7B 13 D8B 14 D9B 15 D10B 16 D11B 17 D12B 18 D13B 20 D14B 21 D15B 22 ORB 24 DCOA 23 DCOB SPI Control 45 SCLK/DFS 44 SDIO/DCS 46 CSB ADC Configuration 47 OEB 48 PDWN ...
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... Channel A/Channel B LVDS Output Data 1—True. Output Channel A/Channel B LVDS Output Data 1—Complement. Output Channel A/Channel B LVDS Output Data 2—True. Output Channel A/Channel B LVDS Output Data 2—Complement. Output Channel A/Channel B LVDS Output Data 3—True. Rev Page AD9650 48 PDWN 47 OEB 46 CSB 45 SCLK/DFS 44 ...
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... AD9650 Pin No. Mnemonic 11 D3− 14 D4+ 13 D4− 16 D5+ 15 D5− 18 D6+ 17 D6− 21 D7+ 20 D7− 23 D8+ 22 D8− 27 D9+ 26 D9− 30 D10+ 29 D10− 32 D11+ 31 D11− 34 D12+ 33 D12− 36 D13+ 35 D13− 39 D14+ 38 D14− 41 D15+ 40 D15− ...
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... Figure 10. AD9650-25 Single-Tone FFT with 9.7 MHz Figure 11. AD9650-25 Single-Tone FFT with 30.3 MHz Figure 12. AD9650-25 Single-Tone FFT with 70.1 MHz Figure 13. AD9650-25 Single-Tone SNR/SFDR vs. Input Amplitude (A IN Rev Page 25MSPS 9.7MHz @ –6dBFS SNR = 77.9dB (83.9dBFS) –20 SFDR = 99dBc –40 –60 –80 –100 –120 –140 0 2 ...
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... SNR (–40°C) 75 SNR (+25°C) SNR (+85°C) SFDR (–40°C) 70 SFDR (+25°C) SFDR (+85° 100 150 200 INPUT FREQUENCY (MHz) Figure 15. AD9650-25 Single-Tone SNR/SFDR vs. Input Frequency (f with 2.7 V p-p Full Scale 105 100 95 SFDR (dBc SNR (dBFS SAMPLE RATE (MSPS) Figure 16 ...
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... TOTAL POWER LVDS (mW) 300 250 TOTAL POWER CMOS (mW) 200 LVDS AND CMOS I 150 100 LVDS I 50 CMOS SAMPLE RATE (MSPS) Figure 20. AD9650-25 Power and Current vs. Sample Rate (mA) AVDD (mA) DRVDD (mA) DRVDD 45 50 Rev Page AD9650 ...
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... FREQUENCY (MHz) Figure 23. AD9650-65 Single-Tone FFT with f 0 –20 –40 –60 –80 –100 –120 –140 9.7 MHz Figure 24. AD9650-65 Single-Tone FFT with –20 –40 –60 –80 –100 –120 –140 Figure 25. AD9650-65 Single-Tone FFT with f = 30.3 MHz IN 0 –20 –40 –60 – ...
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... SNR (dBFS SFDR (dBc –100 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 27. AD9650-65 Single-Tone SNR/SFDR vs. Input Amplitude (A with f =30.3 MHz IN 120 SFDR (dBFS) DITHER ON 115 110 105 100 95 SFDR (dBFS) DITHER OFF 90 SNR (dBFS) DITHER OFF 85 SNR (dBFS) DITHER ON ...
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... Figure 33. AD9650-65 DNL with f 50000 60000 = 9.7 MHz IN Rev Page 700 TOTAL POWER LVDS (mW) 600 500 400 TOTAL POWER CMOS (mW) 300 LVDS AND CMOS I AVDD 200 CMOS I LVDS I (mA) 100 DRVDD SAMPLE RATE (MSPS) Figure 34. AD9650-65 Power and Current vs. Sample Rate (mA) (mA) DRVDD 95 105 ...
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... MHz 30.3 MHz Figure 39. AD9650-80 Single-Tone FFT with f IN 80MSPS 70.1MHz @ –1dBFS SNR = 80dB (81dBFS) SFDR = 86.4dBc Figure 40. AD9650-80 Single-Tone FFT with f = 70.1 MHz IN Rev Page 80MSPS 141MHz @ –1dBFS SNR = 79.3dB (80.3dBFS) –20 SFDR = 79.2dBc –40 –60 –80 –100 –120 – ...
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... IN Rev Page 105 100 95 SFDR 90 85 SNR SAMPLE RATE (MSPS) Figure 44. AD9650-80 Single-Tone SNR/SFDR vs. Sample Rate (f with MHz IN 800000 900000 600000 200000 0 OUTPUT CODE Figure 45. AD9650-80 Grounded Input Histogram 6 DITHER DISABLED DITHER ENABLED –2 –4 –6 0 10000 20000 ...
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... Figure 47. AD9650-80 DNL with f = 9.7 MHz IN 800 700 600 500 400 300 200 CMOS I 100 0 60000 25 35 Figure 48. AD9650-80 Power and Current vs. Sample Rate Rev Page AD9650 TOTAL POWER LVDS (mW) TOTAL POWER CMOS (mW) LVDS AND CMOS I (mA) AVDD LVDS I (mA) (mA) DRVDD DRVDD 45 55 ...
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... FREQUENCY (MHz) Figure 51. AD9650-105 Single-Tone FFT with f 0 –20 –40 –60 –80 –100 –120 –140 9.7 MHz Figure 52. AD9650-105 Single-Tone FFT with –20 –40 –60 –80 –100 –120 –140 30.3 MHz Figure 53. AD9650-105 Single-Tone FFT with –20 –40 –60 – ...
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... SNR (dBFS) DITHER OFF 85 80 SNR (dBFS) DITHER –100 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 56. AD9650-105 Single Tone SNR/SFDR vs. Input Amplitude (A with f = 30.3 MHz with and Without Dither Enabled IN 100 95 SFDR SNR (–40°C) 75 SFDR (–40°C) SNR SNR (+25° ...
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... SFDR (dBFS) –100 –120 IMD3 (dBFS) –140 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 62. AD9650-105 Two-Tone SFDR/IMD3 vs. Input Amplitude ( 128.3 MHz 124.8 MHz, f IN1 IN2 900 TOTAL POWER LVDS (mW) 800 TOTAL POWER CMOS (mW) 700 600 500 400 ...
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... TYPICAL V CM SNR (dBFS) 90 SFDR (dBc 0.80 0.85 0.90 0.95 1.00 1.05 1.10 COMMON-MODE VOLTAGE (V) Figure 67. SNR/SFDR vs. Input Common Mode (VCM) with f = 30.3 MHz IN 1.15 1.20 Rev Page AD9650 ...
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... AD9650 EQUIVALENT CIRCUITS VIN±x Figure 68. Equivalent Analog Input Circuit AVDD 0.9V 10kΩ 10kΩ CLK+ Figure 69. Equivalent Clock Input Circuit DRVDD PAD Figure 70. Digital Output DRVDD 350Ω SDIO/DCS Figure 71. Equivalent SDIO/DCS Circuit DRVDD 350Ω SCLK/DFS OR OEB Figure 72. Equivalent SCLK/DFS or OEB Input Circuit CLK– ...
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... The span of the ADC core is set by this buffer to 2 × VREF. Input Common Mode The analog inputs of the AD9650 are not internally dc biased. In ac-coupled applications, the user must provide this bias exter- nally. Setting the device so that VCM = 0.5 × AVDD (or 0 ...
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... AD8138, ADA4937-2, and provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9650 (see Figure 79), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. ...
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... At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9650. For applications in which SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 81). In this configuration, the input is ac-coupled, and the CML is provided to each input through a 33 Ω ...
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... SELECT LOGIC SENSE Figure 83. Internal Reference Configuration If the internal reference of the AD9650 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 84 shows how the internal reference voltage is affected by loading. Table 11. Refere ...
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... Jitter Considerations section. Figure 87 and Figure 88 show two preferred methods for clocking the AD9650 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun transformer. ...
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... Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and result, may be sensitive to clock duty cycle. The AD9650 requires a tight tolerance on the clock duty cycle to maintain dynamic performance characteristics. The AD9650 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle ...
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... The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9650. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9650 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade. ...
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... AD9650. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9650 signal path. When enabled, the test runs from an internal pseudorandom noise (PN) source through the digital datapath starting at the ADC block output. The BIST sequence runs for 512 cycles and stops ...
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... SERIAL PORT INTERFACE (SPI) The AD9650 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...
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... The pins described in Table 14 comprise the physical interface between the user programming device and the serial port of the AD9650. The SCLK pin and the CSB pin function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...
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... Address 0x17). Default Values After the AD9650 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 17. ...
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... Clock divide Open Open (global) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit Chip ID[7:0] (AD9650 = 0x32, default) Speed grade ID Open Open 001 = 105 MSPS 010 = 80 MSPS 011 = 65 MSPS 100 = 25 MSPS Open Open Open Open Open Open Open ...
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... BIST signature[7:0] BIST signature[15:8] Open Dither Open Open enable Open Open Open Clock divider next SYNC only Rev Page AD9650 Default Default Bit 0 Value Notes/ Bit 1 (LSB) (Hex) Comments 0x00 When this register is set, the test data is placed on the output pins in place of normal data ...
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... AD9650 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. SYNC Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next SYNC Only If the master SYNC enable bit (Address 0x100, Bit 0) and the clock ...
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... LVDS mode. This additional DRVDD current does not cause damage to the AD9650, but it should be taken into account when consid- ering the maximum DRVDD current for the part. To avoid this additional DRVDD current, the AD9650 outputs can be disabled at power-up by taking the OEB pin high ...
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... AD9650BCPZ-105 −40°C to +85°C AD9650BCPZRL7-105 −40°C to +85°C AD9650-25EBZ AD9650-65EBZ AD9650-80EBZ AD9650-105EBZ RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 9.00 BSC SQ 0.60 ...