AD9832BRU Analog Devices Inc, AD9832BRU Datasheet - Page 5

• Manufacturer Part Number: AD9832BRU
• Description: D/A Converter (D-A) IC
• Manufacturer: Analog Devices Inc

Specifications of AD9832BRU

• No. Of Pins: 16
• Peak Reflow Compatible (260 C): No
• No. Of Bits: 10 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 16-TSSOP
• Rohs Status: RoHS non-compliant
• Resolution (bits): 10 b
• Master Fclk: 25MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 2.97 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-AD9832EBZ - BOARD EVAL FOR AD9832
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TIMING CHARACTERISTICS
V
Table 2.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
1
Timing Diagrams
1
2
3
4
5
6
7
8
9
10
11
11A
See the
DD
1
= 3.3 V ± 10%, V
Pin Configuration and Function Descriptions
FSYNC
SDATA
SCLK
Limit at T
40
16
16
50
20
20
15
20
SCLK − 5
15
5
8
8
DD
= 5 V ± 10%, AGND = DGND = 0 V, unless otherwise noted.
MIN
to T
MAX
PSEL0, PSEL1
t
7
(B Version)
D15
FSELECT
MCLK
section.
D14
t
6
VALID DATA
t
5
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
MCLK
Figure 5. Control Timing
t
Figure 3. Master Clock
Figure 4. Serial Timing
4
Rev. B | Page 5 of 24
t
11
D2
t
2
VALID DATA
t
1
t
t
3
9
D1
t
10
Test Conditions/Comments
MCLK period
MCLK high duration
MCLK low duration
SCLK period
SCLK high duration
SCLK low duration
FSYNC to SCLK falling edge setup time
FSYNC to SCLK hold time
Data setup time
Data hold time
FSELECT, PSEL0, PSEL1 setup time before MCLK rising edge
FSELECT, PSEL0, PSEL1 setup time after MCLK rising edge
D0
t
t
8
11A
VALID DATA
D15
D14
AD9832